[PATCH 4/4] arm64: dts: ti: k3-am642-evm/sk: Reserve some on-chip SRAM for R5Fs

[Vignesh Raghavendra]

Hi Suman,

On 5/28/21 8:17 PM, Suman Anna wrote:
> +&oc_sram {
> +	main_r5fss0_core0_sram: r5f-sram at 40000 {
> +		reg = <0x40000 0x40000>;
> +	};
> +
> +	main_r5fss0_core1_sram: r5f-sram at 80000 {
> +		reg = <0x80000 0x40000>;
> +	};
> +
> +	main_r5fss1_core0_sram: r5f-sram at c0000 {
> +		reg = <0xc0000 0x40000>;
> +	};
> +
> +	main_r5fss1_core1_sram: r5f-sram at 100000 {
> +		reg = <0x100000 0x40000>;
> +	};
> +};
> +

Now that ATF is being moved to end of SRAM[1], is it possible to move
these allocations closer to that ATF reserved location?

This will provide one large contiguouos memory at the beginning of SRAM
which can be used as generic pool. Right now there are two
dis-contiguous pool (256K at 0 and ~384K at 140000) which is not very
efficient use of SRAM.


[1]
http://kahuna.dhcp.ti.com:8000/project/arm64-ti-dts/patch/20210607133806.18158-1-a-govindraju@ti.com/