[PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's

[Biju Das]

Hi Prabhakar,

Thanks for the patch.

> Subject: [PATCH v2 11/12] arm64: dts: renesas: Add initial DTSI for
> RZ/G2{L,LC} SoC's
> 
> Add initial DTSI for RZ/G2{L,LC} SoC's.
> 
> File structure:
> r9a07g044.dtsi  => RZ/G2L family SoC common parts r9a07g044l1.dtsi =>
> Specific to RZ/G2L (R9A07G044L single cortex A55) SoC
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Signed-off-by: Biju Das <biju.das.jz at bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r9a07g044.dtsi   | 119 +++++++++++++++++++
>  arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi |  25 ++++
>  2 files changed, 144 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044.dtsi
>  create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> new file mode 100644
> index 000000000000..b2dbf6543d98
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
> @@ -0,0 +1,119 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> +/ {
> +	compatible = "renesas,r9a07g044";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	extal_clk: extal {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0", "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu at 0 {
> +			compatible = "arm,cortex-a55";
> +			reg = <0>;
> +			device_type = "cpu";
> +			next-level-cache = <&L3_CA55>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu1: cpu at 100 {
> +			compatible = "arm,cortex-a55";
> +			reg = <0x100>;
> +			device_type = "cpu";
> +			next-level-cache = <&L3_CA55>;
> +			enable-method = "psci";
> +		};
> +
> +		L3_CA55: cache-controller-0 {
> +			compatible = "cache";
> +			cache-unified;
> +			cache-size = <0x40000>;
> +		};
> +	};
> +
> +	soc: soc {
> +		compatible = "simple-bus";
> +		interrupt-parent = <&gic>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		scif0: serial at 1004b800 {
> +			compatible = "renesas,scif-r9a07g044";
> +			reg = <0 0x1004b800 0 0x400>;
> +			interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "eri", "rxi", "txi",
> +					  "bri", "dri", "tei";
> +			clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>;
> +			clock-names = "fck";
> +			power-domains = <&cpg>;
> +			resets = <&cpg R9A07G044_CLK_SCIF0>;
> +			status = "disabled";
> +		};
> +
> +		cpg: clock-controller at 11010000 {
> +			compatible = "renesas,r9a07g044-cpg";
> +			reg = <0 0x11010000 0 0x10000>;

What about WDTOVF_RST(0xB10) and WDTRST_SEL(0xB14) registers, this registers to be handled by WDT driver.
Unfortunately it is in CPG block.

So do we need to map the entire CPG registers or up to 0xB00?

Geert, Prabhakar: Any thoughts?

Cheers,
Biju

> +			clocks = <&extal_clk>;
> +			clock-names = "extal";
> +			#clock-cells = <2>;
> +			#reset-cells = <1>;
> +			#power-domain-cells = <0>;
> +		};
> +
> +		gic: interrupt-controller at 11900000 {
> +			compatible = "arm,gic-v3";
> +			#interrupt-cells = <3>;
> +			#address-cells = <0>;
> +			interrupt-controller;
> +			reg = <0x0 0x11900000 0 0x40000>,
> +			      <0x0 0x11940000 0 0x60000>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
> | IRQ_TYPE_LEVEL_LOW)>,
> +				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
> IRQ_TYPE_LEVEL_LOW)>,
> +				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
> IRQ_TYPE_LEVEL_LOW)>,
> +				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
> IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> new file mode 100644
> index 000000000000..02f6da806696
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/G2L R9A07G044L1 common parts
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +#include "r9a07g044.dtsi"
> +
> +/ {
> +	compatible = "renesas,r9a07g044l1", "renesas,r9a07g044";
> +
> +	cpus {
> +		/delete-node/ cpu-map;
> +		/delete-node/ cpu at 100;
> +	};
> +
> +	timer {
> +		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1)
> | IRQ_TYPE_LEVEL_LOW)>,
> +				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
> IRQ_TYPE_LEVEL_LOW)>,
> +				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
> IRQ_TYPE_LEVEL_LOW)>,
> +				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
> IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +};
> --
> 2.17.1