[clk:clk-qcom 5/10] drivers/clk/qcom/gcc-mdm9607.c:37:32: warning: unused variable 'gcc_xo_sleep_map'
kernel test robot
lkp at intel.com
Wed Jun 2 20:25:31 PDT 2021
tree: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-qcom
head: ec7e22abec97b6bd577027380077ec395864a3c5
commit: 48b7253264eadc05a3d84db9ea11eef528a0108a [5/10] clk: qcom: Add MDM9607 GCC driver
config: arm64-randconfig-r001-20210603 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project d8e0ae9a76a62bdc6117630d59bf9967ac9bb4ea)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/commit/?id=48b7253264eadc05a3d84db9ea11eef528a0108a
git remote add clk https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
git fetch --no-tags clk clk-qcom
git checkout 48b7253264eadc05a3d84db9ea11eef528a0108a
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>
All warnings (new ones prefixed by >>):
>> drivers/clk/qcom/gcc-mdm9607.c:37:32: warning: unused variable 'gcc_xo_sleep_map' [-Wunused-const-variable]
static const struct parent_map gcc_xo_sleep_map[] = {
^
>> drivers/clk/qcom/gcc-mdm9607.c:42:37: warning: unused variable 'gcc_xo_sleep' [-Wunused-const-variable]
static const struct clk_parent_data gcc_xo_sleep[] = {
^
>> drivers/clk/qcom/gcc-mdm9607.c:116:32: warning: unused variable 'gcc_xo_gpll0_gpll1_map' [-Wunused-const-variable]
static const struct parent_map gcc_xo_gpll0_gpll1_map[] = {
^
>> drivers/clk/qcom/gcc-mdm9607.c:122:37: warning: unused variable 'gcc_xo_gpll0_gpll1' [-Wunused-const-variable]
static const struct clk_parent_data gcc_xo_gpll0_gpll1[] = {
^
4 warnings generated.
vim +/gcc_xo_sleep_map +37 drivers/clk/qcom/gcc-mdm9607.c
36
> 37 static const struct parent_map gcc_xo_sleep_map[] = {
38 { P_XO, 0 },
39 { P_SLEEP_CLK, 6 }
40 };
41
> 42 static const struct clk_parent_data gcc_xo_sleep[] = {
43 { .fw_name = "xo" },
44 { .fw_name = "sleep_clk" },
45 };
46
47 static struct clk_alpha_pll gpll0_early = {
48 .offset = 0x21000,
49 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
50 .clkr = {
51 .enable_reg = 0x45000,
52 .enable_mask = BIT(0),
53 .hw.init = &(struct clk_init_data)
54 {
55 .name = "gpll0_early",
56 .parent_data = &(const struct clk_parent_data){
57 .fw_name = "xo",
58 },
59 .num_parents = 1,
60 .ops = &clk_alpha_pll_ops,
61 },
62 },
63 };
64
65 static struct clk_alpha_pll_postdiv gpll0 = {
66 .offset = 0x21000,
67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
68 .clkr.hw.init = &(struct clk_init_data)
69 {
70 .name = "gpll0",
71 .parent_hws = (const struct clk_hw *[]){ &gpll0_early.clkr.hw },
72 .num_parents = 1,
73 .ops = &clk_alpha_pll_postdiv_ops,
74 },
75 };
76
77 static const struct parent_map gcc_xo_gpll0_map[] = {
78 { P_XO, 0 },
79 { P_GPLL0, 1 },
80 };
81
82 static const struct clk_parent_data gcc_xo_gpll0[] = {
83 { .fw_name = "xo" },
84 { .hw = &gpll0.clkr.hw },
85 };
86
87 static struct clk_pll gpll1 = {
88 .l_reg = 0x20004,
89 .m_reg = 0x20008,
90 .n_reg = 0x2000c,
91 .config_reg = 0x20010,
92 .mode_reg = 0x20000,
93 .status_reg = 0x2001c,
94 .status_bit = 17,
95 .clkr.hw.init = &(struct clk_init_data){
96 .name = "gpll1",
97 .parent_data = &(const struct clk_parent_data){
98 .fw_name = "xo",
99 },
100 .num_parents = 1,
101 .ops = &clk_pll_ops,
102 },
103 };
104
105 static struct clk_regmap gpll1_vote = {
106 .enable_reg = 0x45000,
107 .enable_mask = BIT(1),
108 .hw.init = &(struct clk_init_data){
109 .name = "gpll1_vote",
110 .parent_hws = (const struct clk_hw *[]){ &gpll1.clkr.hw },
111 .num_parents = 1,
112 .ops = &clk_pll_vote_ops,
113 },
114 };
115
> 116 static const struct parent_map gcc_xo_gpll0_gpll1_map[] = {
117 { P_XO, 0 },
118 { P_GPLL0, 1 },
119 { P_GPLL1, 2 },
120 };
121
> 122 static const struct clk_parent_data gcc_xo_gpll0_gpll1[] = {
123 { .fw_name = "xo" },
124 { .hw = &gpll0.clkr.hw },
125 { .hw = &gpll1_vote.hw },
126 };
127
128
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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