[PATCH v2 15/22] dt-bindings: media: camss: Add qcom, sdm660-camss binding
AngeloGioacchino Del Regno
kholk11 at gmail.com
Wed Jan 20 11:17:44 EST 2021
Il giorno mer 20 gen 2021 alle ore 14:44 Robert Foss
<robert.foss at linaro.org> ha scritto:
>
> Add bindings for qcom,sdm660-camss in order to support the camera
> subsystem on SDM630/660 and SDA variants.
>
> Signed-off-by: Robert Foss <robert.foss at linaro.org>
Hey Robert!
> ---
>
> Changes since v1:
> - Laurent: Reworked driver to use dtschema
>
>
> .../bindings/media/qcom,sdm660-camss.yaml | 416 ++++++++++++++++++
> 1 file changed, 416 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml
> new file mode 100644
> index 000000000000..105ce84f9b71
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sdm660-camss.yaml
> @@ -0,0 +1,416 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Qualcomm CAMSS ISP
> +
> +maintainers:
If you want, feel free to add me to the maintainers list for SDM660 CAMSS
- AngeloGioacchino Del Regno <angelogioacchino.delregno at somainline.org>
> + - Robert Foss <robert.foss at linaro.org>
> + - Todor Tomov <todor.too at gmail.com>
> +
> +description: |
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
> +
> +properties:
> + compatible:
> + const: qcom,sdm660-camss
> +
> + clocks:
> + description:
> + Input clocks for the hardware block.
> + minItems: 42
> + maxItems: 42
> +
> + clock-names:
> + description:
> + Names of input clocks for the hardware block.
> + items:
> + - const: ahb
> + - const: cphy_csid0
> + - const: cphy_csid1
> + - const: cphy_csid2
> + - const: cphy_csid3
> + - const: csi0_ahb
> + - const: csi0
> + - const: csi0_phy
> + - const: csi0_pix
> + - const: csi0_rdi
> + - const: csi1_ahb
> + - const: csi1
> + - const: csi1_phy
> + - const: csi1_pix
> + - const: csi1_rdi
> + - const: csi2_ahb
> + - const: csi2
> + - const: csi2_phy
> + - const: csi2_pix
> + - const: csi2_rdi
> + - const: csi3_ahb
> + - const: csi3
> + - const: csi3_phy
> + - const: csi3_pix
> + - const: csi3_rdi
> + - const: csiphy0_timer
> + - const: csiphy1_timer
> + - const: csiphy2_timer
> + - const: csiphy_ahb2crif
> + - const: csi_vfe0
> + - const: csi_vfe1
> + - const: ispif_ahb
> + - const: throttle_axi
> + - const: top_ahb
> + - const: vfe0_ahb
> + - const: vfe0
> + - const: vfe0_stream
> + - const: vfe1_ahb
> + - const: vfe1
> + - const: vfe1_stream
> + - const: vfe_ahb
> + - const: vfe_axi
> +
> + interrupts:
> + description:
> + IRQs for the hardware block.
> + minItems: 10
> + maxItems: 10
> +
> + interrupt-names:
> + description:
> + Names of IRQs for the hardware block.
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid3
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: ispif
> + - const: vfe0
> + - const: vfe1
> +
> + iommus:
> + maxItems: 4
> +
> + power-domains:
> + maxItems: 2
> +
> + ports:
> + description:
> + The CSI data input ports.
> +
> + type: object
> +
> + properties:
> + port at 0:
> + type: object
> + description: Input node for receiving CSI data.
> + properties:
> + endpoint:
> + type: object
> +
> + properties:
> + clock-lanes:
> + description: |-
> + The physical clock lane index.
> +
> + data-lanes:
> + description: |-
> + An array of physical data lanes indexes.
> + Position of an entry determines the logical
> + lane number, while the value of an entry
> + indicates physical lane index.
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + required:
> + - endpoint
> + - reg
> +
> + port at 1:
> + type: object
> + description: Input node for receiving CSI data.
> + properties:
> + endpoint:
> + type: object
> +
> + properties:
> + clock-lanes:
> + description: |-
> + The physical clock lane index.
> +
> + data-lanes:
> + description: |-
> + An array of physical data lanes indexes.
> + Position of an entry determines the logical
> + lane number, while the value of an entry
> + indicates physical lane index.
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + required:
> + - endpoint
> + - reg
> +
> + port at 2:
> + type: object
> + description: Input node for receiving CSI data.
> + properties:
> + endpoint:
> + type: object
> +
> + properties:
> + clock-lanes:
> + description: |-
> + The physical clock lane index.
> +
> + data-lanes:
> + description: |-
> + An array of physical data lanes indexes.
> + Position of an entry determines the logical
> + lane number, while the value of an entry
> + indicates physical lane index.
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + required:
> + - endpoint
> + - reg
> +
> + port at 3:
> + type: object
> + description: Input node for receiving CSI data.
> + properties:
> + endpoint:
> + type: object
> +
> + properties:
> + clock-lanes:
> + description: |-
> + The physical clock lane index.
> +
> + data-lanes:
> + description: |-
> + An array of physical data lanes indexes.
> + Position of an entry determines the logical
> + lane number, while the value of an entry
> + indicates physical lane index.
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
> + required:
> + - endpoint
> + - reg
> +
> + reg:
> + minItems: 14
> + maxItems: 14
> +
> + reg-names:
> + items:
> + - const: csi_clk_mux
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid3
> + - const: csiphy0
> + - const: csiphy0_clk_mux
> + - const: csiphy1
> + - const: csiphy1_clk_mux
> + - const: csiphy2
> + - const: csiphy2_clk_mux
> + - const: ispif
> + - const: vfe0
> + - const: vfe1
> +
> + vdda-supply:
> + description:
> + Definition of the regulator used as analog power supply.
> +
> +required:
> + - clock-names
> + - clocks
> + - compatible
> + - interrupt-names
> + - interrupts
> + - iommus
> + - power-domains
> + - reg
> + - reg-names
> + - vdda-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,gcc-sdm660.h>
> + #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
> +
> + camss: camss at ca00000 {
> + compatible = "qcom,sdm660-camss";
> +
> + clocks = <&mmcc CAMSS_AHB_CLK>,
> + <&mmcc CAMSS_CPHY_CSID0_CLK>,
> + <&mmcc CAMSS_CPHY_CSID1_CLK>,
> + <&mmcc CAMSS_CPHY_CSID2_CLK>,
> + <&mmcc CAMSS_CPHY_CSID3_CLK>,
> + <&mmcc CAMSS_CSI0_AHB_CLK>,
> + <&mmcc CAMSS_CSI0_CLK>,
> + <&mmcc CAMSS_CPHY_CSID0_CLK>,
> + <&mmcc CAMSS_CSI0PIX_CLK>,
> + <&mmcc CAMSS_CSI0RDI_CLK>,
> + <&mmcc CAMSS_CSI1_AHB_CLK>,
> + <&mmcc CAMSS_CSI1_CLK>,
> + <&mmcc CAMSS_CPHY_CSID1_CLK>,
> + <&mmcc CAMSS_CSI1PIX_CLK>,
> + <&mmcc CAMSS_CSI1RDI_CLK>,
> + <&mmcc CAMSS_CSI2_AHB_CLK>,
> + <&mmcc CAMSS_CSI2_CLK>,
> + <&mmcc CAMSS_CPHY_CSID2_CLK>,
> + <&mmcc CAMSS_CSI2PIX_CLK>,
> + <&mmcc CAMSS_CSI2RDI_CLK>,
> + <&mmcc CAMSS_CSI3_AHB_CLK>,
> + <&mmcc CAMSS_CSI3_CLK>,
> + <&mmcc CAMSS_CPHY_CSID3_CLK>,
> + <&mmcc CAMSS_CSI3PIX_CLK>,
> + <&mmcc CAMSS_CSI3RDI_CLK>,
> + <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
> + <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
> + <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
> + <&mmcc CSIPHY_AHB2CRIF_CLK>,
> + <&mmcc CAMSS_CSI_VFE0_CLK>,
> + <&mmcc CAMSS_CSI_VFE1_CLK>,
> + <&mmcc CAMSS_ISPIF_AHB_CLK>,
> + <&mmcc THROTTLE_CAMSS_AXI_CLK>,
> + <&mmcc CAMSS_TOP_AHB_CLK>,
> + <&mmcc CAMSS_VFE0_AHB_CLK>,
> + <&mmcc CAMSS_VFE0_CLK>,
> + <&mmcc CAMSS_VFE0_STREAM_CLK>,
> + <&mmcc CAMSS_VFE1_AHB_CLK>,
> + <&mmcc CAMSS_VFE1_CLK>,
> + <&mmcc CAMSS_VFE1_STREAM_CLK>,
> + <&mmcc CAMSS_VFE_VBIF_AHB_CLK>,
> + <&mmcc CAMSS_VFE_VBIF_AXI_CLK>;
> +
> + clock-names = "ahb",
> + "cphy_csid0",
> + "cphy_csid1",
> + "cphy_csid2",
> + "cphy_csid3",
> + "csi0_ahb",
> + "csi0",
> + "csi0_phy",
> + "csi0_pix",
> + "csi0_rdi",
> + "csi1_ahb",
> + "csi1",
> + "csi1_phy",
> + "csi1_pix",
> + "csi1_rdi",
> + "csi2_ahb",
> + "csi2",
> + "csi2_phy",
> + "csi2_pix",
> + "csi2_rdi",
> + "csi3_ahb",
> + "csi3",
> + "csi3_phy",
> + "csi3_pix",
> + "csi3_rdi",
> + "csiphy0_timer",
> + "csiphy1_timer",
> + "csiphy2_timer",
> + "csiphy_ahb2crif",
> + "csi_vfe0",
> + "csi_vfe1",
> + "ispif_ahb",
> + "throttle_axi",
> + "top_ahb",
> + "vfe0_ahb",
> + "vfe0",
> + "vfe0_stream",
> + "vfe1_ahb",
> + "vfe1",
> + "vfe1_stream",
> + "vfe_ahb",
> + "vfe_axi";
> +
> + interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
> +
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid3",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "ispif",
> + "vfe0",
> + "vfe1";
> +
> + iommus = <&mmss_smmu 0xc00>,
> + <&mmss_smmu 0xc01>,
> + <&mmss_smmu 0xc02>,
> + <&mmss_smmu 0xc03>;
> +
> + power-domains = <&mmcc CAMSS_VFE0_GDSC>,
> + <&mmcc CAMSS_VFE1_GDSC>;
> +
> + reg = <0x0ca00020 0x10>,
> + <0x0ca30000 0x100>,
> + <0x0ca30400 0x100>,
> + <0x0ca30800 0x100>,
> + <0x0ca30c00 0x100>,
> + <0x0c824000 0x1000>,
> + <0x0ca00120 0x4>,
> + <0x0c825000 0x1000>,
> + <0x0ca00124 0x4>,
> + <0x0c826000 0x1000>,
> + <0x0ca00128 0x4>,
> + <0x0ca31000 0x500>,
> + <0x0ca10000 0x1000>,
> + <0x0ca14000 0x1000>;
> +
> + reg-names = "csi_clk_mux",
> + "csid0",
> + "csid1",
> + "csid2",
> + "csid3",
> + "csiphy0",
> + "csiphy0_clk_mux",
> + "csiphy1",
> + "csiphy1_clk_mux",
> + "csiphy2",
> + "csiphy2_clk_mux",
> + "ispif",
> + "vfe0",
> + "vfe1";
> +
> + vdda-supply = <®_2v8>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> --
> 2.27.0
>
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