[PATCH v2 09/15] soc: xilinx: vcu: make pll post divider explicit

[Michal Simek]

On 21. 12. 20 16:06, Michael Tretter wrote:
> According to the downstream driver documentation due to timing
> constraints the output divider of the PLL has to be set to 1/2. Add a
> helper function for that check instead of burying the code in one large
> setup function.
> 
> The bit is undocumented and marked as reserved in the register
> reference.
> 
> Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
> ---
> Changelog:
> 
> v2:
> - Use clk_hw instead of name in xvcu_register_pll_post
> ---
>  drivers/soc/xilinx/xlnx_vcu.c | 51 ++++++++++++++++++++++++-----------
>  1 file changed, 35 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c
> index e38e9c8325a7..6dc58cf58d77 100644
> --- a/drivers/soc/xilinx/xlnx_vcu.c
> +++ b/drivers/soc/xilinx/xlnx_vcu.c
> @@ -81,6 +81,7 @@ struct xvcu_device {
>  	struct regmap *logicore_reg_ba;
>  	void __iomem *vcu_slcr_ba;
>  	struct clk_hw *pll;
> +	struct clk_hw *pll_post;

drivers/soc/xilinx/xlnx_vcu.c:86: warning: Function parameter or member
'pll_post' not described in 'xvcu_device'

Thanks,
Michal