[boot-wrapper] [PATCH] aarch64: Enable TRBE for the non-secure world

[Alexandru Elisei]

Hi,

On 2/12/21 3:44 PM, Suzuki K Poulose wrote:
> On 2/12/21 2:31 PM, Alexandru Elisei wrote:
>> Hello Anshuman,
>>
>> On 2/11/21 11:26 AM, Anshuman Khandual wrote:
>>> MDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace
>>> buffer to use non-secure memory and to permit direct register accesses from
>>> the non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and
>>> make sure TRBE is implemented. We still continue to reset MDCR_EL3 register
>>> to zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB.
>>>
>>> Signed-off-by: Anshuman Khandual <anshuman.khandual at arm.com>
>>> ---
>>>   arch/aarch64/boot.S | 8 ++++++++
>>>   1 file changed, 8 insertions(+)
>>>
>>> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
>>> index 37f4b98..e47cf59 100644
>>> --- a/arch/aarch64/boot.S
>>> +++ b/arch/aarch64/boot.S
>>> @@ -71,6 +71,14 @@ _start:
>>>       ldr    x1, =(0x3 << 12)
>>>       orr    x0, x0, x1
>>>   +1:    mrs    x1, id_aa64dfr0_el1
>>> +    ubfx    x1, x1, #44, #4
>>> +    cbz    x1, 1f
>>> +
>>> +    // Enable TRBE for the non-secure world.
>>> +    ldr    x1, =(0x3 << 24)
>>> +    orr    x0, x0, x1
>>> +
>>>   1:    msr    mdcr_el3, x0            // Disable traps to EL3
>>>         mrs    x0, id_aa64pfr0_el1
>>
>> That's strange, I'm looking at ARM DDI 0487G.a and bits [44:47] from
>> ID_AA64DFR0_EL1 are RES0 and there is no TraceBuffer field; bits [24:25] of
>> MDCR_EL3 are also RES0 and I searched the entire file for the NSTB field, could
>> not find it. Do I have an outdated version of the architecture?
>
> They are not in the Arm ARM. These are part of the Future Architecture
> technology changes, for which the register defintions are available here :
>
> https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/

That worked, thanks!

Thanks,

Alex

>
> Cheers
> Suzuki
>
>>
>> Thanks,
>>
>> Alex
>>
>