[PATCH v3 09/15] soc: xilinx: vcu: make pll post divider explicit

[Stephen Boyd]

Quoting Michael Tretter (2021-01-20 23:16:53)
> According to the downstream driver documentation due to timing
> constraints the output divider of the PLL has to be set to 1/2. Add a
> helper function for that check instead of burying the code in one large
> setup function.
> 
> The bit is undocumented and marked as reserved in the register
> reference.
> 
> Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
> Acked-by: Michal Simek <michal.simek at xilinx.com>
> ---

Applied to clk-next