[PATCH v3 07/15] soc: xilinx: vcu: register PLL as fixed rate clock

[Stephen Boyd]

Quoting Michael Tretter (2021-01-20 23:16:51)
> Currently, xvcu_pll_set_rate configures the PLL to a clock rate that is
> pre-calculated when probing the driver. To still make the clock
> framework aware of the PLL and to allow to configure other clocks based
> on the PLL rate, register the PLL as a fixed rate clock.
> 
> Signed-off-by: Michael Tretter <m.tretter at pengutronix.de>
> Acked-by: Michal Simek <michal.simek at xilinx.com>
> ---

Applied to clk-next