[PATCH 3/5] arm64: atomics: lse: define ANDs in terms of ANDNOTs

[Will Deacon]

On Fri, Dec 10, 2021 at 03:14:08PM +0000, Mark Rutland wrote:
> The FEAT_LSE atomic instructions include atomic bit-clear instructions
> (`ldclr*` and `stclr*`) which can be used to directly implement ANDNOT
> operations. Each AND op is implemented as a copy of the corresponding
> ANDNOT op with a leading `mvn` instruction to apply a bitwise NOT to the
> `i` argument.
> 
> As the compiler has no visibility of the `mvn`, this leads to less than
> optimal code generation when generating `i` into a register. For
> example, __lse_atomic_fetch_and(0xf, v) can be compiled to:
> 
> 	mov     w1, #0xf
> 	mvn     w1, w1
> 	ldclral w1, w1, [x2]
> 
> This patch improves this by replacing the `mvn` with NOT in C before the
> inline assembly block, e.g.
> 
> 	i = ~i;
> 
> This allows the compiler to generate `i` into a register more optimally,
> e.g.
> 
> 	mov     w1, #0xfffffff0
> 	ldclral w1, w1, [x2]
> 
> With this change the assembly for each AND op is identical to the
> corresponding ANDNOT op (including barriers and clobbers), so I've
> removed the inline assembly and rewritten each AND op in terms of the
> corresponding ANDNOT op, e.g.
> 
> | static inline void __lse_atomic_and(int i, atomic_t *v)
> | {
> | 	return __lse_atomic_andnot(~i, v);
> | }
> 
> This is intended as an optimization and cleanup.
> There should be no functional change as a result of this patch.
> 
> Signed-off-by: Mark Rutland <mark.rutland at arm.com>
> Cc: Boqun Feng <boqun.feng at gmail.com>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Peter Zijlstra <peterz at infradead.org>
> Cc: Will Deacon <will at kernel.org>
> ---
>  arch/arm64/include/asm/atomic_lse.h | 34 ++++-------------------------
>  1 file changed, 4 insertions(+), 30 deletions(-)

Acked-by: Will Deacon <will at kernel.org>

Will