[PATCH] coresight: etm4x: fix issues on trcseqevr access

[Mathieu Poirier]

On Wed, Sep 02, 2020 at 06:37:13PM +0800, Jonathan Zhou wrote:
> The TRCSEQEVR(3) is reserved, using '@nrseqstate - 1' instead to avoid
> accessing the reserved register.
> 
> Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
> Cc: Mathieu Poirier <mathieu.poirier at linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose at arm.com>
> Cc: Mike Leach <mike.leach at linaro.org>
> Cc: Shaokun Zhang <zhangshaokun at hisilicon.com>
> Cc: lizixian at hisilicon.com
> 
> Signed-off-by: Jonathan Zhou <jonathan.zhouwen at huawei.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

I have applied this patch.

Thanks,
Mathieu

> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 96425e818fc2..44e44c817bf8 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -1183,7 +1183,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
>  	state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR);
>  	state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR);
>  
> -	for (i = 0; i < drvdata->nrseqstate; i++)
> +	for (i = 0; i < drvdata->nrseqstate - 1; i++)
>  		state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i));
>  
>  	state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR);
> @@ -1288,7 +1288,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>  	writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR);
>  	writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR);
>  
> -	for (i = 0; i < drvdata->nrseqstate; i++)
> +	for (i = 0; i < drvdata->nrseqstate - 1; i++)
>  		writel_relaxed(state->trcseqevr[i],
>  			       drvdata->base + TRCSEQEVRn(i));
>  
> -- 
> 1.9.1
>