[PATCH v2] Coresight: etm4x: add support for Self-hosted trace

[Will Deacon]

[+ Mathieu, since he maintains the driver you're changing]

On Mon, Aug 31, 2020 at 04:02:46PM +0800, Jonathan Zhou wrote:
> ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4
> Self-hosted Trace Extensions. It provides control of exception
> levels and security states. Let's add this feature detection and
> enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is
> supported.
> 
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Will Deacon <will at kernel.org>
> Cc: Suzuki K Poulose <suzuki.poulose at arm.com>
> Cc: Shaokun Zhang <zhangshaokun at hisilicon.com>
> Signed-off-by: Jonathan Zhou <jonathan.zhouwen at huawei.com>
> ---
>  arch/arm64/include/asm/sysreg.h               |  8 ++++++++
>  drivers/hwtracing/coresight/coresight-etm4x.c | 23 +++++++++++++++++++++++
>  2 files changed, 31 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 554a7e8ecb07..53da5f326667 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -184,6 +184,13 @@
>  
>  #define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)
>  
> +/* Trace Filter control */
> +#define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
> +/* Trace is allowed at EL0 */
> +#define SYS_TRFCR_EL1_E0TRE		BIT(0)
> +/* Trace is allowed at EL1 */
> +#define SYS_TRFCR_EL1_E1TRE		BIT(1)

Do we also need to make sure we initialise TRFCR_EL2 correctly for the host?

Will

(keeping rest of the patch intact for Mathieu)

> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 96425e818fc2..f72b457c2bad 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -28,6 +28,7 @@
>  #include <linux/perf_event.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/property.h>
> +#include <asm/sysreg.h>
>  #include <asm/sections.h>
>  #include <asm/local.h>
>  #include <asm/virt.h>
> @@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info)
>  	CS_LOCK(drvdata->base);
>  }
>  
> +static void etm4_init_sysctrl(void *info)
> +{
> +	u64 sys_trfcr_el1, dfr0;
> +	int trace_filt;
> +
> +	dfr0 = read_sysreg(id_aa64dfr0_el1);
> +
> +	trace_filt = cpuid_feature_extract_unsigned_field(dfr0,
> +					ID_AA64DFR0_SELF_HOSTED_SHIFT);
> +	/* if selfhosted trace implemented, enable trace EL0 as default. */
> +	if (trace_filt == 0x1) {
> +		sys_trfcr_el1 = read_sysreg_s(SYS_TRFCR_EL1);
> +		write_sysreg_s(sys_trfcr_el1 | SYS_TRFCR_EL1_E0TRE,
> +				SYS_TRFCR_EL1);
> +		isb();
> +	}
> +}
> +
>  static void etm4_set_default_config(struct etmv4_config *config)
>  {
>  	/* disable all events tracing */
> @@ -1504,6 +1523,10 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
>  				etm4_init_arch_data,  drvdata, 1))
>  		dev_err(dev, "ETM arch init failed\n");
>  
> +	if (smp_call_function_single(drvdata->cpu,
> +				etm4_init_sysctrl, drvdata, 1))
> +		dev_err(dev, "ETM sysctrl init failed\n");
> +
>  	ret = etm4_pm_setup_cpuslocked();
>  	cpus_read_unlock();
>  
> -- 
> 1.9.1
>