[PATCH 10/11] arm64: dts: imx8mm: add GPC node and power domains

[Jacky Bai]

> -----Original Message-----
> From: Adam Ford [mailto:aford173 at gmail.com]
> Sent: Friday, October 23, 2020 9:22 PM
> To: Lucas Stach <l.stach at pengutronix.de>
> Cc: Shawn Guo <shawnguo at kernel.org>; Rob Herring <robh+dt at kernel.org>;
> Marek Vasut <marex at denx.de>; devicetree <devicetree at vger.kernel.org>;
> Frieder Schrempf <frieder.schrempf at kontron.de>;
> patchwork-lst at pengutronix.de; dl-linux-imx <linux-imx at nxp.com>; Sascha
> Hauer <kernel at pengutronix.de>; Fabio Estevam <festevam at gmail.com>;
> arm-soc <linux-arm-kernel at lists.infradead.org>
> Subject: Re: [PATCH 10/11] arm64: dts: imx8mm: add GPC node and power
> domains
> 
> On Wed, Sep 30, 2020 at 10:55 AM Lucas Stach <l.stach at pengutronix.de>
> wrote:
> >
> > This adds the DT nodes to describe the power domains available on the
> > i.MX8MM. Things are a bit more complex compared to other GPCv2 power
> > domain setups, as there is now a hierarchy of domains where complete
> > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also fine
> > granular gating within those subsystems is possible.
> >
> > Note that this is still incomplete, as both VPU and DISP domains are
> > missing their reset clocks. Those aren't directly sourced from the
> > CCM, but have another level of clock gating in the BLKCTL of those
> > domains, which needs a separate driver.
> >
> > Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57
> > +++++++++++++++++++++++
> >  1 file changed, 57 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > index 76f040e4be5e..a841fb2d0458 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > @@ -4,6 +4,8 @@
> >   */
> >
> >  #include <dt-bindings/clock/imx8mm-clock.h>
> > +#include <dt-bindings/power/imx8mm-power.h>
> > +#include <dt-bindings/reset/imx8mq-reset.h>
> >  #include <dt-bindings/gpio/gpio.h>
> >  #include <dt-bindings/input/input.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -547,6 +549,61 @@
> >                                 interrupts = <GIC_SPI 89
> IRQ_TYPE_LEVEL_HIGH>;
> >                                 #reset-cells = <1>;
> >                         };
> > +
> > +                       gpc: gpc at 303a0000 {
> > +                               compatible = "fsl,imx8mm-gpc";
> > +                               reg = <0x303a0000 0x10000>;
> > +                               interrupt-parent = <&gic>;
> > +                               interrupt-controller;
> > +                               #interrupt-cells = <3>;
> 
> Does this need an interrupt index within the GIC?
> possibly something like:   interrupts = <GIC_SPI 87
> IRQ_TYPE_LEVEL_HIGH>;

For imx8m, except imx8mq, we don’t use gpc as interrupt controller anymore, the propterty for gic controller etc are redundant, I think

BR
Jacky Bai
> 
> 
> > +
> > +                               pgc {
> > +                                       #address-cells = <1>;
> > +                                       #size-cells = <0>;
> > +
> > +                                       pgc_hsiomix:
> power-domain at 0 {
> > +
> #power-domain-cells = <0>;
> > +                                               reg =
> <IMX8MM_POWER_DOMAIN_HSIOMIX>;
> > +                                               clocks = <&clk
> IMX8MM_CLK_USB_BUS>;
> > +                                       };
> > +
> > +                                       pgc_pcie:
> power-domain at 1 {
> > +
> #power-domain-cells = <0>;
> > +                                               reg =
> <IMX8MM_POWER_DOMAIN_PCIE>;
> > +                                               power-domains
> = <&pgc_hsiomix>;
> > +                                       };
> > +
> > +                                       pgc_otg1:
> power-domain at 2 {
> > +
> #power-domain-cells = <0>;
> > +                                               reg =
> <IMX8MM_POWER_DOMAIN_OTG1>;
> > +                                               power-domains
> = <&pgc_hsiomix>;
> > +                                       };
> > +
> > +                                       pgc_otg2:
> power-domain at 3 {
> > +
> #power-domain-cells = <0>;
> > +                                               reg =
> <IMX8MM_POWER_DOMAIN_OTG2>;
> > +                                               power-domains
> = <&pgc_hsiomix>;
> > +                                       };
> > +
> > +                                       pgc_gpumix:
> power-domain at 4 {
> > +
> #power-domain-cells = <0>;
> > +                                               reg =
> <IMX8MM_POWER_DOMAIN_GPUMIX>;
> > +                                               clocks = <&clk
> IMX8MM_CLK_GPU_BUS_ROOT>,
> > +
> <&clk IMX8MM_CLK_GPU_AHB>;
> > +                                       };
> > +
> > +                                       pgc_gpu:
> power-domain at 5 {
> > +
> #power-domain-cells = <0>;
> > +                                               reg =
> <IMX8MM_POWER_DOMAIN_GPU>;
> > +                                               clocks = <&clk
> IMX8MM_CLK_GPU_AHB>,
> > +
> <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
> > +
> <&clk IMX8MM_CLK_GPU2D_ROOT>,
> > +
> <&clk IMX8MM_CLK_GPU3D_ROOT>;
> > +                                               resets = <&src
> IMX8MQ_RESET_GPU_RESET>;
> > +                                               power-domains
> = <&pgc_gpumix>;
> > +                                       };
> > +                               };
> > +                       };
> >                 };
> >
> >                 aips2: bus at 30400000 {
> > --
> > 2.20.1
> >
> >
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