[PATCH V3] perf/imx_ddr: Add stop event counters support for i.MX8MP

[Will Deacon]

On Tue, Oct 27, 2020 at 06:44:51PM +0800, Joakim Zhang wrote:
> DDR Perf driver only supports free-running event counters(counter1/2/3)
> now, this patch adds support for stop event counters.
> 
> Legacy SoCs:
> Cycle counter(counter0) is a special counter, only count cycles. When
> cycle counter overflow, it will lock all counters and generate an
> interrupt. In ddr_perf_irq_handler, disable cycle counter then all
> counters would stop at the same time, update all counters' count, then
> enable cycle counter that all counters count again. During this process,
> only clear cycle counter, no need to clear event counters since they are
> free-running counters. They would continue counting after overflow and
> do/while loop from ddr_perf_event_update can handle event counters
> overflow case.
> 
> i.MX8MP:
> Almost all is the same as legacy SoCs, the only difference is that, event
> counters are not free-running any more. Like cycle counter, when event
> counters overflow, they would stop counting unless clear the counter,
> and no interrupt generate for event counters. So we should clear event
> counters that let them re-count when cycle counter overflow, which ensure
> event counters will not lose data.
> 
> This patch adds stop event counters support which would be compatible to
> free-running event counters. We use the cycle counter to stop overflow
> of the event counters.
> 
> Signed-off-by: Joakim Zhang <qiangqing.zhang at nxp.com>
> ---
> ChangeLogs:
> V2->V3:
> 	* return val & CNTL_OVER ? true : false; -> return val &
> 	CNTL_OVER;
> 	* dev_warn() -> dev_warn_ratelimited()
> 	* treat cycle counter and event counter as the same way in
> 	update function.
> 	* add ddr_perf_counter_clear()

Honestly, I've completely lost track of where we are with this driver :(
I guess I'll merge this, and you can fix it if it breaks...

Will