[PATCH v4 24/25] arm64: Add TRFCR_ELx definitions
Catalin Marinas
catalin.marinas at arm.com
Thu Nov 19 12:18:01 EST 2020
On Thu, Nov 19, 2020 at 04:45:46PM +0000, Suzuki K Poulose wrote:
> @@ -988,6 +991,14 @@
> /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
> #define SYS_MPIDR_SAFE_VAL (BIT(31))
>
> +#define TRFCR_ELx_TS_SHIFT 5
> +#define TRFCR_ELx_TS_VIRTUAL ((0x1) << TRFCR_ELx_TS_SHIFT)
> +#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2) << TRFCR_ELx_TS_SHIFT)
> +#define TRFCR_ELx_TS_PHYSICAL ((0x3) << TRFCR_ELx_TS_SHIFT)
For consistency, I'd use 0x1UL etc. in case the shift goes beyond 32
(not the case here though).
Otherwise:
Acked-by: Catalin Marinas <catalin.marinas at arm.com>
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