[PATCH v6 02/26] arm64: mte: CPU feature detection and initial sysreg configuration
Catalin Marinas
catalin.marinas at arm.com
Mon Jul 13 13:45:32 EDT 2020
On Mon, Jul 13, 2020 at 11:08:15AM +0100, Steven Price wrote:
> On 03/07/2020 16:36, Catalin Marinas wrote:
> > From: Vincenzo Frascino <vincenzo.frascino at arm.com>
> >
> > Add the cpufeature and hwcap entries to detect the presence of MTE on
> > the boot CPUs (primary and secondary). Any late secondary CPU not
> > supporting the feature, if detected during boot, will be parked.
> >
> > In addition, add the minimum SCTLR_EL1 and HCR_EL2 bits for enabling
> > MTE. Without subsequent setting of MAIR, these bits do not have an
> > effect on tag checking.
> >
> > Signed-off-by: Vincenzo Frascino <vincenzo.frascino at arm.com>
> > Co-developed-by: Catalin Marinas <catalin.marinas at arm.com>
> > Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> > Cc: Will Deacon <will at kernel.org>
> > Cc: Suzuki K Poulose <Suzuki.Poulose at arm.com>
>
> This commit causes the feature bit to be exposed to a guest, but we
> don't at this point have any way of handling a guest which attempts to
> use MTE.
>
> This is 'fixed' by the first patch of my KVM MTE series[1], but perhaps
> the chunk modifying arch/arm64/kvm/sys_regs.c (see below) should be included here
> instead? That way we hide the feature until we're ready for a guest with
> MTE support.
>
> Steve
> [1] https://lore.kernel.org/r/20200713100102.53664-2-steven.price@arm.com
>
> ----8<----
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index baf5ce9225ce..5ca974c93bd4 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -1104,6 +1104,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
> if (!vcpu_has_sve(vcpu))
> val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
> val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
> + } else if (id == SYS_ID_AA64PFR1_EL1) {
> + val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
> } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
> val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
> (0xfUL << ID_AA64ISAR1_API_SHIFT) |
Thanks Steven. I thought this worked on explicitly enabling the CPUID
for guests but I think I only checked with an old host kernel which was
masking the ID field anyway. I tried it again now and it indeed fails.
I'll fold this in.
--
Catalin
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