[PATCH v8 3/4] phy: Add Sparx5 ethernet serdes PHY driver

[Alexandre Belloni]

On 03/12/2020 22:52:53+0100, Andrew Lunn wrote:
> > +	if (macro->serdestype == SPX5_SDT_6G) {
> > +		value = sdx5_rd(priv, SD6G_LANE_LANE_DF(macro->stpidx));
> > +		analog_sd = SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(value);
> > +	} else if (macro->serdestype == SPX5_SDT_10G) {
> > +		value = sdx5_rd(priv, SD10G_LANE_LANE_DF(macro->stpidx));
> > +		analog_sd = SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(value);
> > +	} else {
> > +		value = sdx5_rd(priv, SD25G_LANE_LANE_DE(macro->stpidx));
> > +		analog_sd = SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(value);
> > +	}
> > +	/* Link up is when analog_sd == 0 */
> > +	return analog_sd;
> > +}
> 
> What i have not yet seen is how this code plugs together with
> phylink_pcs_ops?
> 
> Can this hardware also be used for SATA, USB? As far as i understand,
> the Marvell Comphy is multi-purpose, it is used for networking, USB,
> and SATA, etc. Making it a generic PHY then makes sense, because
> different subsystems need to use it.
> 
> But it looks like this is for networking only? So i'm wondering if it
> belongs in driver/net/pcs and it should be accessed using
> phylink_pcs_ops?
> 

Ocelot had PCie on the phys, doesn't Sparx5 have it?

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com