[PATCH 22/35] arm64: mte: Enable in-kernel MTE

Vincenzo Frascino vincenzo.frascino at arm.com
Thu Aug 27 06:46:07 EDT 2020


On 8/27/20 11:01 AM, Catalin Marinas wrote:
> On Fri, Aug 14, 2020 at 07:27:04PM +0200, Andrey Konovalov wrote:
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index 4d3abb51f7d4..4d94af19d8f6 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -1670,6 +1670,9 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
>>  	write_sysreg_s(0, SYS_TFSR_EL1);
>>  	write_sysreg_s(0, SYS_TFSRE0_EL1);
>>  
>> +	/* Enable Match-All at EL1 */
>> +	sysreg_clear_set(tcr_el1, 0, SYS_TCR_EL1_TCMA1);
>> +
>>  	/*
>>  	 * CnP must be enabled only after the MAIR_EL1 register has been set
>>  	 * up. Inconsistent MAIR_EL1 between CPUs sharing the same TLB may
>> @@ -1687,6 +1690,9 @@ static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
>>  	mair &= ~MAIR_ATTRIDX(MAIR_ATTR_MASK, MT_NORMAL_TAGGED);
>>  	mair |= MAIR_ATTRIDX(MAIR_ATTR_NORMAL_TAGGED, MT_NORMAL_TAGGED);
>>  	write_sysreg_s(mair, SYS_MAIR_EL1);
>> +
>> +	/* Enable MTE Sync Mode for EL1 */
>> +	sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_SYNC);
> 
> In the 8th incarnation of the user MTE patches, this initialisation
> moved to proc.S before the MMU is initialised. When rebasing, please
> take this into account.
> 

Thank you for the heads up.

-- 
Regards,
Vincenzo



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