[PATCH 6/8] arm64: dts: visconti: Add device tree for TMPV7708 RM main board

[Nobuhiro Iwamatsu]

Hi,

Thanks for your review.

On Mon, Aug 17, 2020 at 10:00:45AM +0100, Marc Zyngier wrote:
> On 2020-08-17 02:46, Nobuhiro Iwamatsu wrote:
> > Add basic support for the Visconti TMPV7708 SoC peripherals -
> >   - CPU
> >     - CA53 x 4 and 2 cluster.
> >     - not support PSCI, currently only spin-table is supported.
> 
> We have pushed back on other SoCs in the past when they didn't
> implement PSCI. There really is not good reason not to have
> even the most trivial PSCI implementation these days.

As I've responded to Sudeep Holla, I already understood about this
issue, so I am considering into PSCI support with firmware team.

> 
> >   - Interrupt controller (ARM Generic Interrupt Controller)
> >   - Timer (ARM architected timer)
> >   - UART (ARM PL011 UART controller)
> >   - SPI (ARM PL022 SPI controller)
> >   - I2C (Synopsys DesignWare APB I2C Controller)
> >   - Pin control (Visconti specific)
> > 
> > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu at toshiba.co.jp>
> > ---
> >  arch/arm64/boot/dts/Makefile                  |   1 +
> >  arch/arm64/boot/dts/toshiba/Makefile          |   2 +
> >  .../boot/dts/toshiba/tmpv7708-rm-mbrc.dts     |  44 ++
> >  arch/arm64/boot/dts/toshiba/tmpv7708.dtsi     | 390 ++++++++++++++++++
> >  .../arm64/boot/dts/toshiba/tmpv7708_pins.dtsi |  93 +++++
> >  5 files changed, 530 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/toshiba/Makefile
> >  create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
> >  create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> >  create mode 100644 arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi
> > 
> 
> [...]
> 
> > diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
> > b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
> > new file mode 100644
> > index 000000000000..a883d3ab1858
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
> > @@ -0,0 +1,44 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree File for TMPV7708 RM main board
> > + *
> > + * (C) Copyright 2020, Toshiba Corporation.
> > + * (C) Copyright 2020, Nobuhiro Iwamatsu
> > <nobuhiro1.iwamatsu at toshiba.co.jp>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "tmpv7708.dtsi"
> > +
> > +/ {
> > +	model = "Toshiba TMPV7708 RM main board";
> > +	compatible = "toshiba,tmpv7708-rm-mbrc", "toshiba,tmpv7708";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart1;
> > +	};
> > +
> > +	chosen {
> > +		bootargs = "earlycon=pl011,0x28200000";
> > +		stdout-path = "serial0:115200n8";
> 
> These should be provided by the bootloader, and not hardcoded.
> 

OK, I will remove this line.

> > +	};
> > +
> > +	/* 768MB memory */
> > +	memory at 80000000 {
> > +		device_type = "memory";
> > +		reg = <0x0 0x80000000 0x0 0x30000000>;
> > +	};
> > +};
> > +

<snip>

> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupt-parent = <&gic>;
> > +		always-on;
> 
> That's unlikely to be true. A53 does have low-power modes that
> will kill the comparator, and you will miss timer deadlines.
> This property really only applies to virtual machines, which isn't
> the case here.

I see.
Thank you for the explanation. I remove this parameter.

> 
> > +		interrupts =
> > +			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> > +	};
> > +
> > +	uart_clk: uart-clk {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <150000000>;
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	soc {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		compatible = "simple-bus";
> > +		interrupt-parent = <&gic>;
> > +		ranges;
> > +
> > +		gic: interrupt-controller at 24001000 {
> > +			compatible = "arm,gic-400";
> > +			interrupt-controller;
> > +			#interrupt-cells = <3>;
> > +			reg = <0 0x24001000 0 0x1000>,
> > +			      <0 0x24002000 0 0x2000>,
> > +			      <0 0x24004000 0 0x2000>,
> > +			      <0 0x24006000 0 0x2000>;
> 
> You are missing the maintenance interrupt.

Thanks! I will add interrupts parameter.
> 
> Thanks,
> 
>         M.

Best regards,
  Nobuhiro

> -- 
> Who you jivin' with that Cosmik Debris?
>