[PATCH 20/22] arm64: dts: renesas: r8a77995: draak: enable EthernetAVB

[Yoshihiro Shimoda]

Hello,

> -----Original Message-----
> From: Sergei Shtylyov
> Sent: Saturday, September 30, 2017 7:24 PM
> 
> Hello!
> 
> On 9/29/2017 2:52 PM, Simon Horman wrote:
> 
> > From: Yoshihiro Shimoda <yoshihiro.shimoda.uh at renesas.com>
> >
> > This patch enables EthernetAVB for R-Car D3 draak board.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh at renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>
> > Signed-off-by: Simon Horman <horms+renesas at verge.net.au>
> > ---
> >   arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 25 +++++++++++++++++++++++++
> >   1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > index 7b776cb7e928..96b7ff5cc321 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> > +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
> [...]
> > @@ -37,6 +39,14 @@
> >   };
> >
> >   &pfc {
> > +	avb0_pins: avb {
> > +		mux {
> > +			groups = "avb0_link", "avb0_phy_int", "avb0_mdc",
>                                                ^^^^^^^^^^^^^^
>     Hum, I don't think it's compatible with routing the PHY interrupt via
> GPIO5_19 below. The driver doesn't support signalling via AVB_PHY_INT anyway.

Oops! You're correct. I should drop "avb0_phy_int".

Simon-san, may I send a follow-up patch to fix this?

Best regards,
Yoshihiro Shimoda

> > +				 "avb0_mii";
> > +			function = "avb0";
> > +		};
> > +	};
> > +
> >   	scif2_pins: scif2 {
> >   		groups = "scif2_data";
> >   		function = "scif2";
> > @@ -56,6 +66,21 @@
> >   	status = "okay";
> >   };
> >
> > +&avb {
> > +	pinctrl-0 = <&avb0_pins>;
> > +	pinctrl-names = "default";
> > +	renesas,no-ether-link;
> > +	phy-handle = <&phy0>;
> > +	status = "okay";
> > +
> > +	phy0: ethernet-phy at 0 {
> > +		rxc-skew-ps = <1500>;
> > +		reg = <0>;
> > +		interrupt-parent = <&gpio5>;
> > +		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
> > +	};
> > +};
> > +
> >   &scif2 {
> >   	pinctrl-0 = <&scif2_pins>;
> >   	pinctrl-names = "default";
> 
> MBR, Sergei