[PATCH v3 2/4] clk: gxbb: add the SAR ADC clocks and expose them

[Kevin Hilman]

Stephen Boyd <sboyd at codeaurora.org> writes:

> On 01/19, Martin Blumenstingl wrote:
>> The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks:
>> - a mux clock to choose between different ADC reference clocks (this is
>>   2-bit wide, but the datasheet only lists the parents for the first
>>   bit)
>> - a divider for the input/reference clock
>> - a gate which enables the ADC clock
>> 
>> Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and
>> CLKID_SANA (which seems to enable the analog inputs, but unfortunately
>> there is no documentation for this - we just mimic what the vendor
>> driver does).
>> 
>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
>> Tested-by: Neil Armstrong <narmstrong at baylibre.com>
>> ---
>
> Acked-by: Stephen Boyd <sboyd at codeaurora.org>
>
> This should go through arm-soc along with the other patch to dts.

Applied to v4.11/dt64 of the amlogic tree.

Kevin