[PATCH] ARM: dts: vf610-zii-dev: Add ZII development board.
Stefan Agner
stefan at agner.ch
Tue Feb 23 11:36:49 PST 2016
Hi Andrew,
Some comments below:
On 2016-02-21 11:51, Andrew Lunn wrote:
> From: Cory Tusar <cory.tusar at pid1solutions.com>
>
> This commit adds support for Rev. B of a Zodiac Inflight Innovations
> development board, mainly intended for DSA and ARINC 429 development
> work.
>
> Signed-off-by: Cory Tusar <cory.tusar at pid1solutions.com>
> Signed-off-by: Andrew Lunn <andrew at lunn.ch>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 683 ++++++++++++++++++++++++++++++
> 2 files changed, 685 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index a4a6d70e8b26..47c4c2ff41de 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -372,7 +372,8 @@ dtb-$(CONFIG_SOC_VF610) += \
> vf610m4-colibri.dtb \
> vf610-cosmic.dtb \
> vf610m4-cosmic.dtb \
> - vf610-twr.dtb
> + vf610-twr.dtb \
> + vf610-zii-dev-rev-b.dtb
> dtb-$(CONFIG_ARCH_MXS) += \
> imx23-evk.dtb \
> imx23-olinuxino.dtb \
> diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
> b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
> new file mode 100644
> index 000000000000..fafe0039ebce
> --- /dev/null
> +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
> @@ -0,0 +1,683 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
I recently changed the license of most Vybrid device trees to the new
dual license. Is it possible to change this device tree too?
> +
> +/dts-v1/;
> +#include "vf610.dtsi"
> +
> +/ {
> + model = "ZII VF610 Development Board, Rev B";
> + compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
> +
> + chosen {
> + bootargs = "console=ttyLP0,115200n8";
> + stdout-path = &uart0;
Is bootargs necessary?
For the stdout-path I would recommend to use the advanced format:
stdout-path = "serial0:115200n8";
> + };
> +
> + memory {
> + reg = <0x80000000 0x8000000>;
> + };
> +
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&pinctrl_leds_debug>;
> + pinctrl-names = "default";
> +
> + debug_1 {
> + label = "zii:green:debug1";
> + gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + mdio-mux {
> + compatible = "mdio-mux-gpio";
> + pinctrl-0 = <&pinctrl_mdio_mux>;
> + pinctrl-names = "default";
> + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
> + &gpio0 9 GPIO_ACTIVE_HIGH
> + &gpio0 24 GPIO_ACTIVE_HIGH
> + &gpio0 25 GPIO_ACTIVE_HIGH>;
> + mdio-parent-bus = <&mdio1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mdio_mux_1: mdio at 1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
Since there are no child nodes the #address- and #size-cells properties
are not necessary.
> + };
> +
> + mdio_mux_2: mdio at 2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mdio_mux_4: mdio at 4 {
> + reg = <4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mdio_mux_8: mdio at 8 {
> + reg = <8>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + dsa at 0 {
> + compatible = "marvell,dsa";
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + dsa,ethernet = <&fec1>;
> + dsa,mii-bus = <&mdio_mux_1>;
> +
> + /* 6352 - Primary - 7 ports */
> + switch0: switch at 2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x00 0>;
> + eeprom-length = <512>;
> +
> + port at 0 {
> + reg = <0>;
> + label = "lan0";
> + };
> +
> + port at 1 {
> + reg = <1>;
> + label = "lan1";
> + };
> +
> + port at 2 {
> + reg = <2>;
> + label = "lan2";
> + };
> +
> + switch0port5: port at 5 {
> + reg = <5>;
> + label = "dsa";
> + phy-mode = "rgmii-txid";
> + link = <&switch1port6
> + &switch2port9>;
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port at 6 {
> + reg = <6>;
> + label = "cpu";
> + fixed-link {
> + speed = <100>;
> + full-duplex;
> + };
> + };
> +
> + };
> +
> + /* 6352 - Secondary - 7 ports */
> + switch1: switch at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x00 1>;
> + eeprom-length = <512>;
> + mii-bus = <&mdio_mux_2>;
> +
> + port at 0 {
> + reg = <0>;
> + label = "lan3";
> + };
> +
> + port at 1 {
> + reg = <1>;
> + label = "lan4";
> + };
> +
> + port at 2 {
> + reg = <2>;
> + label = "lan5";
> + };
> +
> + switch1port5: port at 5 {
> + reg = <5>;
> + label = "dsa";
> + link = <&switch2port9>;
> + phy-mode = "rgmii-txid";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + switch1port6: port at 6 {
> + reg = <6>;
> + label = "dsa";
> + phy-mode = "rgmii-txid";
> + link = <&switch0port5>;
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> + };
> +
> + /* 6185 - 10 ports */
> + switch2: switch at 6 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x00 2>;
> + mii-bus = <&mdio_mux_4>;
> +
> + port at 0 {
> + reg = <0>;
> + label = "lan6";
> + };
> +
> + port at 1 {
> + reg = <1>;
> + label = "lan7";
> + };
> +
> + port at 2 {
> + reg = <2>;
> + label = "lan8";
> + };
> +
> + port at 3 {
> + reg = <3>;
> + label = "optical3";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + link-gpios = <&gpio6 2
> + GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + port at 4 {
> + reg = <4>;
> + label = "optical4";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + link-gpios = <&gpio6 3
> + GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + switch2port9: port at 9 {
> + reg = <9>;
> + label = "dsa";
> + phy-mode = "rgmii-txid";
> + link = <&switch1port5
> + &switch0port5>;
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> + };
> + };
> +
> + audio_ext: mclk-osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24576000>;
> + };
This seems not to be used anywhere. Maybe needs to be assigned to the
clks node?
> +
> + enet_ext: eth-osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + };
Same here...
> +
> + reg_3p3v: regulator at 0 {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
Do not use the address format (@0) in node name if the regulator is not
part of a bus.
Use regulator-3p3v as node name.
> +
> + reg_vcc_3v3_mcu: regulator at 1 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_3v3_mcu";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + usb0_vbus: regulator at 2 {
> + compatible = "regulator-fixed";
> + pinctrl-0 = <&pinctrl_usb_vbus>;
> + regulator-name = "usb_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + regulator-always-on;
> + regulator-boot-on;
> + gpio = <&gpio0 6 0>;
> + };
> +};
> +
> +&fec0 {
> + phy-mode = "rmii";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec0>;
> + status = "okay";
> +};
> +
> +&fec1 {
> + phy-mode = "rmii";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + status = "okay";
> +
> + fixed-link {
> + speed = <100>;
> + full-duplex;
> + };
> +
> + mdio1: mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> + };
> +};
> +
> +&adc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_adc0_ad5>;
> + vref-supply = <®_vcc_3v3_mcu>;
> + status = "okay";
> +};
> +
> +&edma0 {
> + status = "okay";
> +};
> +
> +&esdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_esdhc1>;
> + bus-width = <4>;
> + status = "okay";
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c0>;
> + status = "okay";
> +
> + gpio5: pca9505 at 20 {
> + compatible = "nxp,pca9554";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + };
> +
> + gpio6: pca9505 at 22 {
> + compatible = "nxp,pca9554";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pca9554_opt>;
> + reg = <0x22>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
> + };
Hm, any reason why one of this is a gpio-controller while the other
isn't?
> +
> + lm75 at 48 {
> + compatible = "national,lm75";
> + reg = <0x48>;
> + };
> +
> + at24c04 at 50 {
> + compatible = "atmel,24c04";
> + reg = <0x50>;
> + };
> +
> + at24c04 at 52 {
> + compatible = "atmel,24c04";
> + reg = <0x52>;
> + };
> +
> + ds1682 at 6b {
> + compatible = "dallas,ds1682";
> + reg = <0x6b>;
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + tca9548 at 70 {
> + compatible = "nxp,pca9548";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x70>;
> + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
> +
> + i2c2_0: i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + sfp1: at24c04 at 50 {
> + compatible = "atmel,24c02";
> + reg = <0x50>;
> + };
> + };
> +
> + i2c2_1: i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + sfp2: at24c04 at 50 {
> + compatible = "atmel,24c02";
> + reg = <0x50>;
> + };
> + };
> +
> + i2c2_2: i2c at 2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> +
> + sfp3: at24c04 at 50 {
> + compatible = "atmel,24c02";
> + reg = <0x50>;
> + };
> + };
> +
> + i2c2_3: i2c at 3 {
There is an extra space between the colon and i2c at 3...
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> +
> + sfp4: at24c04 at 50 {
> + compatible = "atmel,24c02";
> + reg = <0x50>;
> + };
> +
> + };
> +
> + i2c2_4: i2c at 4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + };
> + };
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + status = "okay";
> +};
> +
> +&iomuxc {
We normally put the iomuxc node at the very end.
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c_mux_reset>;
> +
> + vf610-zii {
> + pinctrl_usb_vbus: pinctrl-usb-vbus {
> + fsl,pins = <
> + VF610_PAD_PTA16__GPIO_6 0x31c2
> + >;
> + };
> +
> + pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
> + fsl,pins = <
> + VF610_PAD_PTE14__GPIO_119 0x31c2
> + >;
> + };
> +
> + pinctrl_adc0_ad5: adc0ad5grp {
> + fsl,pins = <
> + VF610_PAD_PTC30__ADC0_SE5 0x00a1
> + >;
> + };
> +
> + pinctrl_esdhc1: esdhc1grp {
> + fsl,pins = <
> + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
> + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
> + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
> + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
> + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
> + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
> + VF610_PAD_PTA7__GPIO_134 0x219d
> + >;
> + };
> +
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + VF610_PAD_PTA6__RMII_CLKIN 0x30d1
> + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
> + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
> + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
> + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
> + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
> + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
> + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
> + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
> + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
> + >;
> + };
> +
> + pinctrl_i2c0: i2c0grp {
> + fsl,pins = <
> + VF610_PAD_PTB14__I2C0_SCL 0x37ff
> + VF610_PAD_PTB15__I2C0_SDA 0x37ff
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + VF610_PAD_PTB16__I2C1_SCL 0x37ff
> + VF610_PAD_PTB17__I2C1_SDA 0x37ff
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + VF610_PAD_PTA22__I2C2_SCL 0x37ff
> + VF610_PAD_PTA23__I2C2_SDA 0x37ff
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + VF610_PAD_PTA30__I2C3_SCL 0x37ff
> + VF610_PAD_PTA31__I2C3_SDA 0x37ff
> + >;
> + };
> +
> + pinctrl_pwm0: pwm0grp {
> + fsl,pins = <
> + VF610_PAD_PTB0__FTM0_CH0 0x1582
> + VF610_PAD_PTB1__FTM0_CH1 0x1582
> + VF610_PAD_PTB2__FTM0_CH2 0x1582
> + VF610_PAD_PTB3__FTM0_CH3 0x1582
> + >;
> + };
> +
> + pinctrl_uart0: uart0grp {
> + fsl,pins = <
> + VF610_PAD_PTB10__UART0_TX 0x21a2
> + VF610_PAD_PTB11__UART0_RX 0x21a1
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + VF610_PAD_PTB23__UART1_TX 0x21a2
> + VF610_PAD_PTB24__UART1_RX 0x21a1
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + VF610_PAD_PTD0__UART2_TX 0x21a2
> + VF610_PAD_PTD1__UART2_RX 0x21a1
> + >;
> + };
> +
> + pinctrl_qspi0: qspi0grp {
> + fsl,pins = <
> + VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3
> + VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff
> + VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3
> + VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3
> + VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3
> + VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3
> + >;
> + };
> +
> + pinctrl_usb0_host: usb0-host-grp {
> + fsl,pins = <
> + VF610_PAD_PTD6__GPIO_85 0x0062
> + >;
> + };
> + pinctrl_mdio_mux: pinctrl-mdio-mux {
> + fsl,pins = <
> + VF610_PAD_PTA18__GPIO_8 0x31c2
> + VF610_PAD_PTA19__GPIO_9 0x31c2
> + VF610_PAD_PTB2__GPIO_24 0x31c2
> + VF610_PAD_PTB3__GPIO_25 0x31c2
> + >;
> + };
> + pinctrl_fec0: fec0grp {
> + fsl,pins = <
> + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2
> + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3
> + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
> + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
> + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
> + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
> + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
> + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
> + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
> + >;
> + };
> +
> + pinctrl_leds_debug: pinctrl-leds-debug {
> + fsl,pins = <
> + VF610_PAD_PTD20__GPIO_74 0x31c2
> + >;
> + };
> +
> + pinctrl_pca9554_opt: pinctrl-pca95540-opt {
> + fsl,pins = <
> + VF610_PAD_PTB18__GPIO_40 0x219d
> + >;
> + };
> + };
> +};
> +
> +&L2 {
> + arm,data-latency = <2 1 2>;
> + arm,tag-latency = <3 2 3>;
> +};
Are you sure about that?
With 9c17190595 ("ARM: dts: vf610: use reset values for L2 cache
latencies") we have reasonable values in the base device tree
vf610.dtsi, I think therefor this is not necessary anymore, even if you
use 500MHz as CPU clock.
--
Stefan
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart0>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + status = "okay";
> +};
> +
> +&usbdev0 {
> + disable-over-current;
> + status = "okay";
> + vbus-supply = <&usb0_vbus>;
> + dr_mode = "host";
> +};
> +
> +&usbh1 {
> + disable-over-current;
> + status = "okay";
> +};
> +
> +&usbmisc0 {
> + status = "okay";
> +};
> +
> +&usbmisc1 {
> + status = "okay";
> +};
> +
> +&usbphy0 {
> + status = "okay";
> +};
> +
> +&usbphy1 {
> + status = "okay";
> +};
> +
> +&qspi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi0>;
> + fsl,nor-size = <0x10000000>;
> + fsl,spi-num-chipselects = <2>;
> + status = "okay";
> +
> + flash0: mt25ql02gc at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "micron,mt25ql02gc";
> + spi-max-frequency = <66000000>;
> + reg = <0>;
> +
> + partition at 0 {
> + label = "mt25ql02gc-0-uboot";
> + reg = <0x0 0x0100000>;
> + };
> +
> + partition2 at 100000 {
> + label = "mt25ql02gc-0-dtb";
> + reg = <0x0100000 0x0100000>;
> + };
> +
> + partition3 at 200000 {
> + label = "mt25ql02gc-0-kernel";
> + reg = <0x0200000 0x0500000>;
> + };
> +
> + partition4 at 700000 {
> + label = "mt25ql02gc-0-rfs";
> + reg = <0x0600000 0x8000000>;
> + };
> + };
> +};
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