[PATCH v2] arm64: dts: r8a7795: Add L2 cache-controller nodes

[Simon Horman]

[CC new linux-renesas-soc ML]

Hi Dirk,

On Wed, Feb 03, 2016 at 06:21:17PM +0100, Dirk Behme wrote:
> On 16.01.2016 15:17, Dirk Behme wrote:
> >From: Geert Uytterhoeven <geert+renesas at glider.be>
> >
> >Add device nodes for the L2 caches, and link the CPU node to its L2
> >cache node.
> >
> >The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
> >128 KiB x 16 ways).
> >
> >Signed-off-by: Geert Uytterhoeven <geert+renesas at glider.be>
> >Signed-off-by: Dirk Behme <dirk.behme at gmail.com>

[snip]

> Any further comments to this? If not, could this be applied?

Sorry for the delay.

This looks good; I have queued it up.

It should appear in the next (and devel) branches of my renesas tree soon.
And in linux-next whenever it includes my updated next branch.