[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

[Hans de Goede]

Hi,

On 01-08-16 15:52, Jean-Francois Moine wrote:
> On Sat, 30 Jul 2016 12:19:03 +0200
> Hans de Goede <hdegoede at redhat.com> wrote:
>
>> Jean-Francois, can you submit a v2 of your patch and make the writing of
>> SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ?
>>
>> Also you should probably drop the bits about the clock stuff from the
>> commit message as that just seems to confuse people.
>
> Hi Hans,
>
> I submitted a new patch (sorry, I forgot the history), but it asks for
> some explanation.
>
> - in the old timings, the phase delays are set in the clock.
>   That's why there is a function clk_set_phase() which is called from
>   the MMC side.
>
> - in the new timings, the delays are in the MMC register SDXC_REG_NTSR
>   only.
>   In this case, the function clk_set_phase() is of no use
>   (also, by test, it seems that the phase delays set by hardware
>    reset do work, so, there is no need to set them), but,
>
> - there is a bit in the clock telling that the new timings are used,
>   i.e. that the phase delays of the clock must be ignored.
>
>   Not setting this bit prevents the device to work (at least in the
>   A83T, the H3 seems more helpful).

Thanks for the explanation, it would be good to put this in the commit
msg of v3 of the patch.

Regards,

Hans