[PATCHv4 23/24] arm64: Expose feature registers by emulating MRS
Dave.Martin at arm.com
Wed Oct 21 01:50:17 PDT 2015
On Mon, Oct 19, 2015 at 02:25:00PM +0100, Suzuki K. Poulose wrote:
> This patch adds the hook for emulating MRS instruction to
> export the 'user visible' value of supported system registers.
> We emulate only the following id space for system registers:
> Op0=0, Op1=0, CRn=0.
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 896a821..c44da31 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -908,3 +910,106 @@ void __init setup_cpu_features(void)
> pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
> L1_CACHE_BYTES, cls);
> + * We emulate only the following system register space.
> + * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0 - 7]
nit: ^ whitespace, no need to fix unless respinning the series
> + * With CRm = 0, id should be one of :
> + * MIDR_EL1
> + * MPIDR_EL1
> + * REVIDR_EL1
nit: ^ whitespace
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