[PATCH] arm64: Increase the max granular size
timur at codeaurora.org
Fri Oct 16 12:57:30 PDT 2015
On Tue, Sep 22, 2015 at 12:59 PM, Robert Richter <rric at kernel.org> wrote:
> From: Tirumalesh Chalamarla <tchalamarla at cavium.com>
> Increase the standard cacheline size to avoid having locks in the same
> Cavium's ThunderX core implements cache lines of 128 byte size. With
> current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could
> share the same cache line leading a performance degradation.
> Increasing the size fixes that.
> Increasing the size has no negative impact to cache invalidation on
> systems with a smaller cache line. There is an impact on memory usage,
> but that's not too important for arm64 use cases.
> Signed-off-by: Tirumalesh Chalamarla <tchalamarla at cavium.com>
> Signed-off-by: Robert Richter <rrichter at cavium.com>
Acked-by: Timur Tabi <timur at codeaurora.org>
We need this patch, because on our silicon, CTR_EL0[CWG] set to 5, which
means that setup_processor() complains with this warning:
cls = cache_line_size();
if (L1_CACHE_BYTES < cls)
pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule
(%d < %d)\n",
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