[PATCH v3 05/12] doc/bindings: Update Layerscape PCIe devicetree binding to be more flexible
arnd at arndb.de
Thu Oct 15 07:16:57 PDT 2015
On Thursday 15 October 2015 12:17:45 Bhupesh Sharma wrote:
> +Note that since this controller derives its clocks from the Reset
> +Configuration Word (RCW) which is used to describe the PLL settings at
> +the time of chip-reset, the 'clocks' and 'clock-names' properties from
> +'designware-pcie.txt' are optional for this controller.
If this is an option for the dw-pcie block, should this description be
added to the generic binding instead?
> +Also as per the available Reference Manuals, there is no specific 'version'
> +register available in the Freescale PCIe controller register set,
> +which can allow determining the underlying Designware PCIe controller version
> Required properties:
> -- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
> +- compatible: should contain the platform identifier such as "fsl,<soc-name>-pcie",
> + "snps,dw-pcie".
You should document all the strings that will be needed here, otherwise a
driver write does not know what to look for.
If two chips have a 100% identical PCIe implementation, just use the string
of the older chip for both.
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