[PATCH v4 2/4] drivers: clk: st: PLL rate change implementation for DVFS

Stephen Boyd sboyd at codeaurora.org
Wed Oct 7 12:14:59 PDT 2015

On 10/07, Gabriel Fernandez wrote:
> Change A9 PLL rate, as per requirement from the cpufreq framework,
> for DVFS. For rate change, the A9 clock needs to be temporarily sourced
> from PLL external to A9 and then sourced back to A9-PLL
> Signed-off-by: Pankaj Dev <pankaj.dev at st.com>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez at linaro.org>
> ---

Applied to clk-next

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