[PATCH v7 5/6] Documentation: dt-bindings: pci: altera pcie device tree binding

Ley Foon Tan lftan at altera.com
Sun Oct 4 20:14:05 PDT 2015

On Sat, Oct 3, 2015 at 5:56 AM, Arnd Bergmann <arnd at arndb.de> wrote:
> On Friday 02 October 2015 15:53:44 Ley Foon Tan wrote:
>> > Strictly speaking, if you have undocumented bindings downstream that
>> > is your problem and we don't have to accept them as-is upstream. I'm
>> > not going to worry about that here.
>> >
>> >>> txs contains the config space?
>> >> It is not the config space, but a memory slave port.
>> >
>> > Then where is the config space? It should not be part of "ranges" is
>> > all I care about.
>> The config space is not part of "ranges". Our IP uses TLP packet to
>> access config space.
> It took me a bit to figure out what you mean here. To save others
> from reading the source, here is what I found:
> * The config space is accessed indirectly through registers from the
>   "cra" register range, which is the right approach according to the
>   point that Rob made.
You are right.

> * hardware-wise this basically looks like bit-banged PCIe, which is
>   both awesome and scary ;-)

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