[PATCH] clk: sunxi: pll2: Fix clock running too fast

[Maxime Ripard]

On Mon, Nov 30, 2015 at 11:32:16AM -0800, Stephen Boyd wrote:
> On 11/30, Maxime Ripard wrote:
> > @@ -191,25 +186,17 @@ err_unmap:
> >  	iounmap(reg);
> >  }
> >  
> > -static struct sun4i_pll2_data sun4i_a10_pll2_data = {
> > -	.pre_div_flags	= CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
> > -};
> > -
> >  static void __init sun4i_a10_pll2_setup(struct device_node *node)
> >  {
> > -	sun4i_pll2_setup(node, &sun4i_a10_pll2_data);
> > +	sun4i_pll2_setup(node, &sun4i_a10_pll2_data, 0);
> 
> And it doesn't compile, because we just deleted the data that
> this is taking an address of. Hmph.

Sorry for the screw up, I'll resend a new version tomorrow...

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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