[PATCH] arm64: mm: Prevent the initial page table setup from creating larger blocks
jeremy.linton at arm.com
Wed Nov 25 08:31:48 PST 2015
On 11/24/2015 11:48 AM, Catalin Marinas wrote:
> While the ARM ARM is not entirely clear, over the years we have assumed
> that we can split a large block entry (pmd/pud) into smaller blocks
> pointing to the same physical address with little risk of a TLB
> conflict. However, remapping a smaller blocks range as a large one (e.g.
> from page to sections or to contiguous pages) implies a high risk of TLB
> conflict. Excessive TLB flushing would make the window smaller but it
> would not remove the issue.
Is a requirement of this assumption, that the kernel isn't running on a
VM'ed host with small page mappings? AKA the hypervisor is providing
smaller page sizes than guest linear mapping?
Because I can understand the idea that the CPU won't walk PTEs for
entries it has a larger translation for, but my understanding of how the
TLB's are fragmented when the host has a smaller page size means that
its potentially possible to have multiple TLB entries for different
parts of a single cont/block range....
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