Minimal support for dm814x
Matthijs van Duin
matthijsvanduin at gmail.com
Tue Nov 10 02:44:31 PST 2015
On 10 November 2015 at 11:23, Delio Brignoli <dbrignoli at audioscience.com> wrote:
> are you aware of section 2.1.2 of ...
I am. It seems that the digital PLLs tend to produce an asymmetrical
clock in general hence you need an even postdivider to get a 50% duty
cycle. DPLL-S however already has an implicit /2 divider integrated,
and a few peripherals seem to be fine with an asymmetrical clock (e.g.
apparently the USB subsystem which is clocked by PLL_USB / 5).
In the most recent SoCs they included a "DC corrector" in some PLLs to
be able to symmetrize the clock without the need for postdivision.
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