[RFC] ARM: exynos: MCPM: [is this a] fix for secondary boot on 5422?
p.marczak at samsung.com
Mon Jun 15 07:00:21 PDT 2015
On 06/15/2015 02:17 PM, Krzysztof Kozłowski wrote:
> 2015-06-15 19:19 GMT+09:00 Przemyslaw Marczak <p.marczak at samsung.com>:
>> Hello Krzysztof,
>> On 06/14/2015 10:56 AM, Krzysztof Kozłowski wrote:
>>> +Cc Marek, Bartlomiej, Kukjin Kim,
>>> I would like to bring back this topic. Unfortunately I don't have
>>> access to source code of BL1 (or any other firmware blob) so my
>>> knowledge here comes mostly from experimenting and from looking at
>>> sources of vendor kernel for Gear 2 (Exynos3250) and SM-G900H (Galaxy
>>> S5, Exynos5422).
>>> It seems that some booting firmware (I would suspect BL1 because this
>>> ships Samsung to Hardkernel) uses SPARE2 as synchronization mechanism.
>>> For example vendor kernel, when booting little core, it waits till
>>> SPARE2==1 and then executes software reset for this core.
>>> Observations shown that BL1 for Odroid, when booting secondary little
>>> 1. Expects that SPARE2 register will be initialized to 1.
>>> 2. If it is, then it sets it to 0, proceeds further and little core boots.
>>> 3. If it is not, then it sets it to 1 and waits. Maybe this is a
>>> notification to userspace - reset me please!
>>> Unfortunately executing software reset in that time (at point 3)
>>> stopped kernel from booting. No logs/dmesg and I was unable to turn on
>>> early printk.
>>> The answer why two of little cores boot is quite simple now. At
>>> beginning the SPARE2==0 so first little core will set it to 1 and wait
>>> till software reset. Kernel timeouts on this CPU bring up so it starts
>>> the sequence for next little core. Now the SPARE2==1 so the core boots
>>> fine and SPARE2 is set to 0. The last little core starts from
>>> SPARE2==0, sets it to 1 and waits for software reset.
>>> Since no one knows how this exactly works and we are stuck with BL1
>>> provided as is, then IMHO the patch makes sense.
>>> Kevin, can you refresh the patch?
>>> It would be nice to:
>>> 1. set SPARE2 only for Odroid (of_machine_is_compatible()),
>>> 2. extend the explanation.
>>> Best regards,
>> I'm trying port the hardkernel's SPL to the mainline U-Boot at present. The
>> mainline SPL is implemented for E5420 and E5800. But there are few
>> - different DRAM
>> - different clocks
>> - different boot core (peach-pi boots from A15)
>> - bl2 signature
>> - hdk's SPL uses smc calls
>> ... and some more.
>> The BL1 keeps signature key and some part of code, but it's code is
>> proprietary - but we should be able to setup the secondary cores in BL2.
>> When, I get the basic setup working, then I'm going to focus on the
>> secondary CPU's init. I don't have the documentation for iROM code, so
>> everything takes a while.
> Great, good luck!
>> If you looking for the lowlevel code, which is executed after wakeup,
>> please check this :
>> The 'lowlevel_init' label is always executed on boot.
> I already looked at it without any success. I couldn't find the reason
> of this SPARE2 behaviour in that code. However I found there one small
> funny fact about magic values for low power modes - kernel and u-boot
> expect some of the values in different places.
> Best regards,
I checked the SPARE registers, and only SPARE0 is set by iROM code to
0xFCBA0D10, it is defined in the kernel as: S5P_CHECK_AFTR. I didn't
analyzed the kernel code yet, however it looks, that it doesn't use
I need finish the basic SPL support, and then will start synchronize
with the kernel.
Samsung R&D Institute Poland
p.marczak at samsung.com
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