[PATCH] arm64: dts: Fix GIC reg sizes for APM X-Gene

[Rob Herring]

On Tue, Jan 27, 2015 at 1:03 AM, Pranavkumar Sawargaonkar
<psawargaonkar at apm.com> wrote:
> In APM X-Gene, GIC register space is 64K aligned while the sizes mentioned
> in the dt are 4K aligned. This breaks KVM when kernel is built with 64K page
> size due to size alignment checking in vgic driver for VCPU Control and
> VCPU register.
>
> This patch corrects the sizes to be inline with the hardware spec.

This does not make sense. The GIC regions are still only 4 or 8KB and
the h/w description should reflect that. For implementations using
gic-400 and the addressing decode trick, the rest of the register
range is also not safe to access given it is multiple mapped. Also,
this wastes virtual space, but I guess we don't care on 64-bit.

KVM should be fixed to only check base address alignment. Size
alignment does not matter (if it does, then you need to fix all
register blocks).

Rob

>
> CC: linux-arm-kernel at lists.infradead.org
> CC: kvmarm at lists.cs.columbia.edu
> CC: arnd at arndb.de
> CC: marc.zyngier at arm.com
> CC: christoffer.dall at linaro.org
> CC: jcm at redhat.com
> Signed-off-by: Pranavkumar Sawargaonkar <psawargaonkar at apm.com>
> Signed-off-by: Tushar Jagad <tjagad at apm.com>
> Signed-off-by: Feng Kan <fkan at apm.com>
> ---
>  arch/arm64/boot/dts/apm/apm-storm.dtsi |    8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
> index f1ad9c2..65f0e6d 100644
> --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
> +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
> @@ -81,10 +81,10 @@
>                 compatible = "arm,cortex-a15-gic";
>                 #interrupt-cells = <3>;
>                 interrupt-controller;
> -               reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
> -                     <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
> -                     <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
> -                     <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
> +               reg = <0x0 0x78010000 0x0 0x10000>,     /* GIC Dist */
> +                     <0x0 0x78020000 0x0 0x20000>,     /* GIC CPU */
> +                     <0x0 0x78040000 0x0 0x10000>,     /* GIC VCPU Control */
> +                     <0x0 0x78060000 0x0 0x20000>;     /* GIC VCPU */
>                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
>         };
>
> --
> 1.7.9.5
>
>
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