[PATCH] i2c: designware: prevent early stop on TX FIFO empty

Mika Westerberg mika.westerberg at linux.intel.com
Wed Nov 19 06:18:34 PST 2014

On Wed, Nov 19, 2014 at 10:21:22AM +0100, Wolfram Sang wrote:
> On Fri, Nov 07, 2014 at 12:10:44PM +0000, Andrew Jackson wrote:
> > If the Designware core is configured with IC_EMPTYFIFO_HOLD_MASTER_EN
> > set to zero, allowing the TX FIFO to become empty causes a STOP
> > condition to be generated on the I2C bus. If the transmit FIFO
> > threshold is set too high, an erroneous STOP condition can be
> > generated on long transfers - particularly where the interrupt
> > latency is extended.

Makes sense to give some slack so that the interrupt handler is still
able to fill the FIFO.

> > 
> > Signed-off-by: Andrew Jackson <Andrew.Jackson at arm.com>
> > Signed-off-by: Liviu Dudau <Liviu.Dudau at arm.com>
> So, what do other designware users think of this change (nice CC list
> BTW, Andrew). Adding Mika, too.

I quickly tested this on Haswell machine with touch screen connected to
the I2C bus and it still works fine, so

Tested-by: Mika Westerberg <mika.westerberg at linux.intel.com>

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