[PATCH] arm/arm64: KVM: Handle traps of ICC_SRE_EL1 as RAZ/WI

Marc Zyngier marc.zyngier at arm.com
Wed Nov 19 03:13:07 PST 2014

On Wed, Nov 19 2014 at 11:02:29 am GMT, Ard Biesheuvel <ard.biesheuvel at linaro.org> wrote:
> From: Christoffer Dall <christoffer.dall at linaro.org>
> When running on a system with a GICv3, we currenly don't allow the guest
> to access the system register interface of the GICv3.  We do this by
> clearing the ICC_SRE_EL2.Enable, which causes all guest accesses to
> ICC_SRE_EL1 to trap to EL2 and causes all guest accesses to other ICC_
> registers to cause an undefined exception in the guest.
> However, we currently don't handle the trap of guest accesses to
> ICC_SRE_EL1 and will spill out a warning.  The trap just needs to handle
> the access as RAZ/WI, and a guest that tries to prod this register and
> set ICC_SRE_EL1.SRE=1, must read back the value (which Linux already
> does) to see if it succeeded, and will thus observe that ICC_SRE_EL1.SRE
> was not set.
> Add the simple trap handler in the sorted table of the system registers.
> Signed-off-by: Christoffer Dall <christoffer.dall at linaro.org>
> [ardb: added 32-bit counterpart]
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel at linaro.org>
> --
> v2: added 32-bit counterpart, renaming pm_fake to trap_raz_wi in the process,
>     hence the additional changes on that side
> ---
>  arch/arm/kvm/coproc.c     | 49 +++++++++++++++++++++++++----------------------
>  arch/arm64/kvm/sys_regs.c |  5 +++++
>  2 files changed, 31 insertions(+), 23 deletions(-)

Err... Not really. What I meant was to update the cp15_regs array in
arch/arm64/kvm/sys_regs.c. The 32bit port of KVM is unlikely to ever
grow support for GICv3, as these registers are *not* defined for ARMv7.


Jazz is not dead. It just smells funny.

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