[PATCHv3 5/5] arm64: Trace emulation of AArch32 legacy instructions

[Punit Agrawal]

Hi Will,

Thanks for taking a look.

Will Deacon <will.deacon at arm.com> writes:

> On Mon, Oct 27, 2014 at 06:40:07PM +0000, Punit Agrawal wrote:
>> Introduce an event to trace the usage of emulated instructions. The
>> trace event is intended to help identify and encourage the migration
>> of legacy software using the emulation features.
>> 
>> Use this event to trace usage of swp and CP15 barrier emulation.
>> 
>> Cc: Steven Rostedt <rostedt at goodmis.org>
>> Signed-off-by: Punit Agrawal <punit.agrawal at arm.com>
>> ---

[...]

>> @@ -260,16 +268,23 @@ static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
>>  		 * dmb - mcr p15, 0, Rt, c7, c10, 5
>>  		 * dsb - mcr p15, 0, Rt, c7, c10, 4
>>  		 */
>> -		if (aarch32_insn_mcr_extract_opc2(instr) == 5)
>> +		if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
>>  			dmb(sy);
>> -		else
>> +			trace_instruction_emulation(
>> +				"mcr p15, 0, Rt, c7, c10, 5", regs->pc);
>> +		} else {
>>  			dsb(sy);
>> +			trace_instruction_emulation(
>> +				"mcr p15, 0, Rt, c7, c10, 4", regs->pc);
>> +		}
>>  		break;
>>  	case 5:
>>  		/*
>>  		 * isb - mcr p15, 0, Rt, c7, c5, 4
>>  		 */
>>  		isb();
>> +		trace_instruction_emulation(
>> +			"mcr p15, 0, Rt, c7, c5, 4", regs->pc);
>
> Any chance you can put the barrier name in here too please? Maybe as an asm
> comment, e.g.:
>
>   "mcr p15, 0, Rt, c7, c5, 4 ; isb"

Good point. I've added the barrier names as assembler comments.

Thanks.

>
> Will
>
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