[PATCH 4/7] can: m_can: add a bit delay after setting CCCR_INIT bit

Marc Kleine-Budde mkl at pengutronix.de
Mon Nov 3 08:52:11 PST 2014

On 10/29/2014 11:45 AM, Dong Aisheng wrote:
> The spec mentions there may be a delay until the value written to
> INIT can be read back due to the synchronization mechanism between the
> two clock domains. But it does not indicate the exact clock cycles needed.
> The 5us delay is a test value and seems ok.
> Without the delay, CCCR.CCE bit may fail to be set and then the
> initialization fail sometimes when do repeatly up and down.
> Signed-off-by: Dong Aisheng <b29396 at freescale.com>

Applied to can/master.


Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
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