[RFC PATCH 2/2] ARM: imx6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority

[Fabio Estevam]

On Thu, Feb 20, 2014 at 8:44 AM, Philipp Zabel <p.zabel at pengutronix.de> wrote:
> This is needed so that the IPU framebuffer scanout cannot be
> starved by VPU or GPU activity.
> Some boards like the SabreLite and SabreSD seem to set this in
> the DCD already, but the documented register reset values do not
> contain the necessary settings.
>
> Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>

Yes, better to configure it in the kernel than relying on the
bootloader to do this setup.

Reviewed-by: Fabio Estevam <fabio.estevam at freescale.com>