[PATCH 3/3] dmaengine: sirf: enable the driver support new SiRFmarco SoC

Barry Song 21cnbao at gmail.com
Thu Oct 25 01:25:45 EDT 2012


2012/10/25 Vinod Koul <vkoul at infradead.org>:
> On Wed, 2012-10-24 at 19:59 +0800, Barry Song wrote:
>> Hi Vinod,
>> Thanks a lot!
> Please dont top post.

well. saying hello is an exception :-)

>>
>> 2012/10/24 Vinod Koul <vkoul at infradead.org>
>> >
>> > On Thu, 2012-09-27 at 16:36 +0800, Barry Song wrote:
>> > > From: Barry Song <Baohua.Song at csr.com>
>> > >
>> > > The driver supports old up SiRFprimaII SoCs, this patch makes it support
>> > > the new SiRFmarco as well.
>> > > SiRFmarco, as a SMP SoC, adds new DMA_INT_EN_CLR and DMA_CH_LOOP_CTRL_CLR
>> > > registers, to disable IRQ/Channel, we should write 1 to the corresponding
>> > > bit in the two CLEAR register.
>> > >
>> > > Tested on SiRFmarco using SPI driver:
>> > >     $ /mnt/spidev-sirftest -D /dev/spidev32766.0
>> > >     spi mode: 0
>> > >     bits per word: 8
>> > >     max speed: 500000 Hz (500 KHz)
>> > >
>> > >     00 00 00 00 00 00
>> > >     00 00 00 00 00 00
>> > >     00 00 00 00 00 00
>> > >     00 00 00 00 00 00
>> > >     00 00 00 00 00 00
>> > >     00 00 00 00 00 00
>> > >     00 00 00 00
>> > >
>> > >     $ cat /proc/interrupts
>> > >                CPU0       CPU1
>> > >      32:       1593          0       GIC  sirfsoc_timer0
>> > >      33:          0       3533       GIC  sirfsoc_timer1
>> > >      44:          0          0       GIC  sirfsoc_dma
>> > >      45:         16          0       GIC  sirfsoc_dma
>> > >      47:          6          0       GIC  sirfsoc_spi
>> > >      50:       5654          0       GIC  sirfsoc-uart
>> > >      ...
>> > >
>> > > Signed-off-by: Barry Song <Baohua.Song at csr.com>
>> > > ---
> I tried applying this and it failed for me. Can you please respin this
> on my next and send again.

ok
>
> --
> Vinod Koul
> Intel Corp.

-barry



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