[PATCH] i2c i.MX: Fix divider table

[Richard Zhao]

On Wed, Jul 11, 2012 at 08:38:38PM +0200, Sascha Hauer wrote:
> Hi Richard,
> 
> On Wed, Jul 11, 2012 at 02:01:21PM +0800, Richard Zhao wrote:
> > 
> > IC guys confirmed that the spec is right:
> > 
> > This an adaptive feature of our I2C module may apply to all IMX chips.
> > No mistake in the table of RMs.
> > 
> > The divider is designed to guarantee SCL high level and low level last
> > time. Divider will hold when SCL transition from 1 to 0 or 0 to 1, if
> > the transition time is longer than 1 internal pre-divided clock cycle.
> > The pre-divided clock is divided from I2C module clock, used for
> > generating SCL. So you will see SCL clock cycle is some way longer than
> > calculated value using IFDR.
> > 
> > Transition time will different from rising or falling edge, different
> > pull-up resistors, and different SCL loading.
> > 
> > This feature make sure transition time won’t eat both level time of SCL.
> 
> Thanks for clarification. Does this mean that this feature is used to
> synchronize between the bus clock and and bitclock?
Per my understanding,
Not exactly. Divided clock is only used for count time of SCL level
hold. This means, even if the i2c bus loading is high (long level
setup time), the i2c may still work.

Thanks
Richard
> 
> I'll send a documentation patch for this next week to make this clear.
> 
> Sascha
> 
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