[RFC 3/6] arm: cache-l2x0: add support for Aurora L2 cache ctrl

[Will Deacon]

On Fri, Aug 10, 2012 at 04:13:41PM +0100, Gregory CLEMENT wrote:
> On 08/10/2012 04:49 PM, Will Deacon wrote:
> > Can the Armada 370 be configured to use the co-processor interface to the
> > L2, or does only the Armada XP support that feature? What happens if you
> > build a single zImage supporting both of the SoCs?
> 
> About L2 cache we already use the same kernel on Armada 370 and Armada XP
> and the differences are in the device tree.

Right, but I wonder whether you can end up using both the outer_cache
functions *and* the co-processor interface on the Armada XP by accident.
Ideally, we'd just use the co-processor interface on all platforms and
ignore the memory-mapped one. Is that possible on the 370?

> Now if I understood correctly what the LPAE involved, I guess we can't have
> a kernel with LAPE running on Armada 370.

Indeed, but you could still run with 2-level page tables on both SoCs (with
less memory on the XP).

Will