SPI subsystem delays

[Jassi Brar]

On 23 April 2012 02:37, Matt Wood <mattwood2000 at gmail.com> wrote:
>
> has some specific delay requirements - specifically
> the delay between bytes in a single transfer
>
Sounds like your chip specific quirk. Apparently throughput would
be the last of your concerns :D
Perhaps you have to do single byte transfers with appropriate
non-zero 'delay_usecs' and skilfully toggle 'cs_change' for
each transfer.

> delay between chip select assertion and the first clock edge
>
IMO that could already be done from within your controller driver.

> and the delay between consecutive transfers.
>
Why not spi_transfer.delay_usecs ?

-jassi