Identifying Primecells

[jonsmirl at gmail.com]

On Sat, Sep 24, 2011 at 7:15 PM, Vitaly Wool <vitalywool at gmail.com> wrote:
> Hi,
>
> On Fri, Sep 23, 2011 at 9:11 PM, jonsmirl at gmail.com <jonsmirl at gmail.com> wrote:
>> On Fri, Sep 23, 2011 at 10:22 AM, Pawel Moll <pawel.moll at arm.com> wrote:
>>>> My registers don't seem to match up with the pl011 documentation...
>>> <...>
>>>> INTCE W       0xFD8   Interrupt       Clear Enable Register
>>>> INTSE W       0xFDC   Interrupt       Set Enable Register
>>>> INTS  R       0xFE0   Interrupt       Status Register
>>>> INTE  R       0xFE4   Interrupt       Enable Register
>>>
>>> ... nor any other PrimeCell, actually :-)
>>>
>>> "Compliant" PrimeCells must have the PCellID in the last 4 registers:
>>
>> I scanned though 0xff0/f for all of the devices. The only one that had
>> anything that makes sense is the Multiport Memory Controller -
>> 0xb105f00d
>>
>> So it looks like NXP made almost all of their own peripherals. Which
>> means I have to clean up the drivers for all of them.
>>
>
> I have a vague recollection that some time ago NXP was using UARTs
> that were basically 8250-compatible but with some twist. You may also
> want to check the pnx8xxx_uart implementation for another type of
> UARTs NXP used to have on their MIPS boards.

I have a driver for the chip. It is a 8250 compatible that has been
extended with DMA support.

I've drivers for all of the peripherals on the chip. As I start
sending them out for RFC maybe we can identify them as variants of
drivers already in the kernel so that I don't add 20 new drivers if
some are redundant.

-- 
Jon Smirl
jonsmirl at gmail.com