[PATCH] ARM: Improve the L2 cache performance when PL310 is used

[Catalin Marinas]

On Tue, 2011-02-15 at 11:29 +0000, Srinidhi Kasagar wrote:
> Just curious to know, why the spinlock surrounding
> l2x0_cache_sync still exists?  I see that
> Catalin's first version adds void lock for PL310
> as they are atomic.

On PL310, range operations and the cache sync don't need the spinlock.
However, TI pushed optimisations to use "all" operations for large
ranges. These operations are background and you need to use a cache sync
until completed. You also need locks around since starting other
operations while a background one is active is unpredictable.

-- 
Catalin