[PATCH] ARM: errata: pl310 cache sync operation may be faulty

[Russell King - ARM Linux]

On Tue, Feb 15, 2011 at 04:48:03PM +0530, srinidhi kasagar wrote:
> +#ifdef ARM_ERRATA_753970
> +#define L2X0_DUMMY_REG  0x740
> +	/* write to an unmmapped register */
> +	writel_relaxed(0, base + L2X0_DUMMY_REG);
> +	cache_wait(base + L2X0_CACHE_SYNC, 1);
> +#else
>  	writel_relaxed(0, base + L2X0_CACHE_SYNC);
>  	cache_wait(base + L2X0_CACHE_SYNC, 1);
> +#endif

So why wrap cache_wait() up in that horrible ifdef as well - and why not
put the dummy register definition along side the other register definitions?