[PATCH AUTOSEL 6.19-6.18] clk: amlogic: remove potentially unsafe flags from S4 video clocks

[Sasha Levin]

From: Chuan Liu <chuan.liu at amlogic.com>

[ Upstream commit 4aca7e92023cac5018b4053bae324450f884c937 ]

The video clocks enci, encp, vdac and hdmitx share the same clock
source. Adding CLK_SET_RATE_PARENT to the mux may unintentionally change
the shared parent clock, which could affect other video clocks.

Signed-off-by: Chuan Liu <chuan.liu at amlogic.com>
Link: https://lore.kernel.org/r/20250919-add_video_clk-v6-3-fe223161fb3f@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet at baylibre.com>
Signed-off-by: Sasha Levin <sashal at kernel.org>
---

LLM Generated explanations, may be completely bogus:

Wait, this is very confusing. The mailing list says patch 2 adds new
clocks, but git blame shows these video clock muxes (`cts_enci_sel`,
`cts_encp_sel`, etc.) were already in the original commit from 2023. Let
me re-read the diff more carefully.

Looking at the diff again: the commit removes `CLK_SET_RATE_PARENT` from
`s4_cts_enci_sel`, `s4_cts_encp_sel`, `s4_cts_vdac_sel`, and
`s4_hdmi_tx_sel`. Git blame confirmed these structures were added in
`57b55c76aaf1b` (2023, v6.7). The patch 2 of the series adds **new**
clocks (encl, cdac, demod, adc), but the ones being **fixed** in patch 3
already existed.

This means patch 3 (our commit) is **self-contained** with respect to
the bug fix — it removes flags from clocks that already exist in stable
trees. It does NOT depend on patch 2.

## Final Analysis

### Problem Description
The `CLK_SET_RATE_PARENT` flag on the video clock mux selectors
(`cts_enci_sel`, `cts_encp_sel`, `cts_vdac_sel`, `hdmi_tx_sel`) allows
rate change requests to propagate from these muxes up to their shared
parent clock. Since all four muxes share the same parent clock sources
(vclk_div and vclk2_div families), any one of them requesting a rate
change could alter the parent, breaking the other video outputs.

### Impact Assessment
- **Real bug**: Yes — when one video output (e.g., HDMI) requests a
  clock rate change, it can modify the shared parent clock, causing
  other video outputs (CVBS, encoder) to use the wrong clock rate. This
  could result in display corruption or loss of video signal.
- **Scope**: Affects all Amlogic S4 SoC users with multiple active video
  outputs, since v6.7.
- **Severity**: Medium — display corruption/failure when multiple video
  outputs are active simultaneously.

### Stable Kernel Criteria Assessment
- **Obviously correct**: Yes — removing `CLK_SET_RATE_PARENT` from
  shared mux selectors is a well-understood pattern for preventing
  unintended parent clock modifications.
- **Fixes a real bug**: Yes — prevents unintended shared parent clock
  modification affecting other video clocks.
- **Small and contained**: Yes — removes 4 lines (flag declarations)
  from a single file.
- **No new features**: Correct — purely a bug fix.
- **Risk**: Very low — removing `CLK_SET_RATE_PARENT` means the mux
  won't propagate rate changes upward, which is the desired behavior for
  shared clock sources. The downstream gate clocks still have
  `CLK_SET_RATE_PARENT`, so rate requests still propagate from the gate
  to the mux; they just stop there instead of going further up.

### Concerns
- **Dependency check**: The fix is self-contained. The affected clock
  structures exist since v6.7 (commit `57b55c76aaf1b`). No dependency on
  other patches in the series.
- **Behavioral change**: Users who relied on `CLK_SET_RATE_PARENT`
  propagation through the mux to the parent might see different
  behavior, but this "reliance" was always incorrect since it could
  break other video outputs.

## Verification

- **git blame** confirmed `s4_cts_enci_sel`, `s4_cts_encp_sel`,
  `s4_cts_vdac_sel`, `s4_hdmi_tx_sel` with `CLK_SET_RATE_PARENT` were
  introduced in `57b55c76aaf1b` (v6.7, September 2023).
- **git tag --contains 57b55c76aaf1b** confirmed the buggy code is in
  v6.7+ and v6.12.y LTS.
- **lore.kernel.org** confirmed this is patch 3/3 of the "add video-
  related clocks for S4 SoC" series, accepted December 2025 by Jerome
  Brunet.
- **lore.kernel.org patch 2** confirmed patch 2 adds **different**
  clocks (encl, cdac, demod, adc), not the ones being fixed here — the
  fix is independent.
- **Code inspection** confirmed `s4_cts_encl_sel` already lacked
  `CLK_SET_RATE_PARENT` (consistent architecture — encl was already
  correct).
- **Code inspection** confirmed downstream gate clocks (`s4_cts_enci`,
  `s4_cts_encp`) retain `CLK_SET_RATE_PARENT`, so rate propagation still
  works from gate to mux but stops at the mux level.
- **Could NOT verify** any user reports of actual display corruption
  from this bug (unverified — but the mechanism is sound and the fix is
  obvious).

The fix is small, surgical, self-contained, fixes a real clock-tree
correctness issue affecting all Amlogic S4 users since v6.7, and carries
extremely low regression risk. It meets all stable kernel criteria.

**YES**

 drivers/clk/meson/s4-peripherals.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peripherals.c
index 6d69b132d1e1f..bab4f5700de47 100644
--- a/drivers/clk/meson/s4-peripherals.c
+++ b/drivers/clk/meson/s4-peripherals.c
@@ -1106,7 +1106,6 @@ static struct clk_regmap s4_cts_enci_sel = {
 		.ops = &clk_regmap_mux_ops,
 		.parent_hws = s4_cts_parents,
 		.num_parents = ARRAY_SIZE(s4_cts_parents),
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -1122,7 +1121,6 @@ static struct clk_regmap s4_cts_encp_sel = {
 		.ops = &clk_regmap_mux_ops,
 		.parent_hws = s4_cts_parents,
 		.num_parents = ARRAY_SIZE(s4_cts_parents),
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -1138,7 +1136,6 @@ static struct clk_regmap s4_cts_vdac_sel = {
 		.ops = &clk_regmap_mux_ops,
 		.parent_hws = s4_cts_parents,
 		.num_parents = ARRAY_SIZE(s4_cts_parents),
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -1169,7 +1166,6 @@ static struct clk_regmap s4_hdmi_tx_sel = {
 		.ops = &clk_regmap_mux_ops,
 		.parent_hws = s4_hdmi_tx_parents,
 		.num_parents = ARRAY_SIZE(s4_hdmi_tx_parents),
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
-- 
2.51.0