[PATCH v2 02/11] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC

[Krzysztof Kozlowski]

On 25/08/2025 08:51, Anand Moon wrote:
> As per S905X3 datasheet add missing cache information to the Amlogic
> SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache.
> 
> - Each Cortex-A55 core has 32KB of L1 instruction cache available and
> 	32KB of L1 data cache available.
> - Along with 256KB Unified L2 cache.
> 
> Cache memory significantly reduces the time it takes for the CPU
> to access data and instructions, leading to faster program execution
> and overall system responsiveness.


This statement is obvious and completely redundant. Drop it from all of
the commits.

Best regards,
Krzysztof