[LEDE-DEV] [RFC] ipq806x: Add USB Type Selector for R7500

[Thomas Reifferscheid]

The patch enables the primary USB port on R7500. Because of the
missing general IPQ8064x TCSR initialisation functions a workaround
using pinctrl,single was chosen. It allows us to set 1a4000b0 from
0000.0010 to 0000.0011 thus enabling the primary USB port - prior
to the dwc3-phy initialisation. Needs to be reworked once Qualcomm
adds TCSR initialisation functionality from their 3.x kernel into 4.x
kernels.

The patch fixes FS#497 and partially backs off
45bf3d4f248ea2d770a1625fdee8899dc40329af which had the right idea but
was missing the syscon-tcsr handler - which by the time of the upstream
patch attempt (January 2015) was trying to set the TCSR USB Type
selector at the wrong part of the kernel.

Signed-off-by: Thomas Reifferscheid <thomas at reifferscheid.org>
---
 ...ipq806x-add-usbtypesel-required-for-r7500.patch | 56 ++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 target/linux/ipq806x/patches-4.4/716-ipq806x-add-usbtypesel-required-for-r7500.patch

diff --git a/target/linux/ipq806x/patches-4.4/716-ipq806x-add-usbtypesel-required-for-r7500.patch b/target/linux/ipq806x/patches-4.4/716-ipq806x-add-usbtypesel-required-for-r7500.patch
new file mode 100644
index 0000000..4927708
--- /dev/null
+++ b/target/linux/ipq806x/patches-4.4/716-ipq806x-add-usbtypesel-required-for-r7500.patch
@@ -0,0 +1,56 @@
+diff -Naur a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi	2017-02-27 12:34:58.669161969 +0100
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi	2017-02-27 12:40:51.253172676 +0100
+@@ -626,6 +626,13 @@
+ 			reg = <0x1a400000 0x100>;
+ 		};
+ 
++                usbtypesel: pinmux at 1a4000b0 {
++                        compatible = "pinctrl-single";
++                        pinctrl-single,register-width = <32>;   /* u32                          */
++                        pinctrl-single,function-mask = <0x03>;  /* only allow to set the 2 LSBs */
++                        reg = <0x1a4000b0 0x04>;                /* u32                          */
++                };
++
+ 		lcc: clock-controller at 28000000 {
+ 			compatible = "qcom,lcc-ipq8064";
+ 			reg = <0x28000000 0x1000>;
+@@ -685,8 +692,6 @@
+ 			clocks = <&gcc USB30_0_MASTER_CLK>;
+ 			clock-names = "core";
+ 
+-			syscon-tcsr = <&tcsr 0xb0 1>;
+-
+ 			ranges;
+ 
+ 			status = "disabled";
+@@ -709,8 +714,6 @@
+ 			clocks = <&gcc USB30_1_MASTER_CLK>;
+ 			clock-names = "core";
+ 
+-			syscon-tcsr = <&tcsr 0xb0 0>;
+-
+ 			ranges;
+ 
+ 			status = "disabled";
+diff -Naur a/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
+--- a/arch/arm/boot/dts/qcom-ipq8064-r7500.dts	2017-02-27 12:35:08.693162274 +0100
++++ b/arch/arm/boot/dts/qcom-ipq8064-r7500.dts	2017-02-27 12:35:12.677162395 +0100
+@@ -131,6 +131,17 @@
+ 			status = "ok";
+ 		};
+ 
++                pinmux at 1a4000b0 {
++                        pinctrl-names = "default";
++                        pinctrl-0 = <&board_pins>;
++
++                        board_pins: pinmux_board_pins {
++                                pinctrl-single,pins = <
++                                        0x00 0x03 /* IPQ_TCSR_USB_CONTROLLER_TYPE_SEL TCSR_USB_SELECT_USB3_DUAL */
++                                >;
++                        };
++                };
++
+ 		phy at 100f8800 {		/* USB3 port 1 HS phy */
+ 			status = "ok";
+ 		};
-- 
2.1.4