[openwrt/openwrt] ar71xx: kernel: enable PCI on QCA9556 SoC

[LEDE Commits]

dangole pushed a commit to openwrt/openwrt.git, branch master:
https://git.lede-project.org/20e68f6d395d72ca8a5d5ec364bc7cf4c1862b87

commit 20e68f6d395d72ca8a5d5ec364bc7cf4c1862b87
Author: Roger Pueyo Centelles <roger.pueyo at guifi.net>
AuthorDate: Mon Jan 8 12:30:28 2018 +0100

    ar71xx: kernel: enable PCI on QCA9556 SoC
    
    This patch enables the PCI bus on the QCA9556 SoC, the same way it is
    done on the same family SoC QCA9558.
    
    Tested on a MikroTik RouterBoard wAPG-5HacT2HnD (wAP AC).
    
    Signed-off-by: Roger Pueyo Centelles <roger.pueyo at guifi.net>
---
 .../patches-4.4/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch | 12 ++++++++++++
 .../patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch | 12 ++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/target/linux/ar71xx/patches-4.4/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch b/target/linux/ar71xx/patches-4.4/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch
new file mode 100644
index 0000000..3a6438e
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.4/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch
@@ -0,0 +1,12 @@
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -324,7 +324,8 @@ int __init ath79_register_pci(void)
+						 QCA953X_PCI_MEM_SIZE,
+						 0,
+						 ATH79_IP2_IRQ(0));
+-	} else if (soc_is_qca9558()) {
++	} else if (soc_is_qca9558() ||
++		   soc_is_qca9556()) {
+		pdev = ath79_register_pci_ar724x(0,
+						 QCA955X_PCI_CFG_BASE0,
+						 QCA955X_PCI_CTRL_BASE0,
diff --git a/target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch b/target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch
new file mode 100644
index 0000000..3a6438e
--- /dev/null
+++ b/target/linux/ar71xx/patches-4.9/741-MIPS-ath79-add-PCI-for-QCA9556-SoC.patch
@@ -0,0 +1,12 @@
+--- a/arch/mips/ath79/pci.c
++++ b/arch/mips/ath79/pci.c
+@@ -324,7 +324,8 @@ int __init ath79_register_pci(void)
+						 QCA953X_PCI_MEM_SIZE,
+						 0,
+						 ATH79_IP2_IRQ(0));
+-	} else if (soc_is_qca9558()) {
++	} else if (soc_is_qca9558() ||
++		   soc_is_qca9556()) {
+		pdev = ath79_register_pci_ar724x(0,
+						 QCA955X_PCI_CFG_BASE0,
+						 QCA955X_PCI_CTRL_BASE0,