[RFC] mci: imx-esdhc-pbl: enable ADMA2 for i.MX8M BL33 loads

[Johannes Schneider]

Hoi Ahmad,

> > On 6/19/26 6:09 PM, Johannes Schneider wrote:
> > Add a generic sdhci_enable_adma() helper that lets drivers provide their own
> > descriptor table (so PBL builds can use a static buffer without dma_alloc),
>
> On Rockchip, we already allocate an early malloc pool. I'd rather see
> that we do the same on i.MX PBL as well instead of switching over to
> static buffers.

ACK - early malloc pool rather than the static table, if this comes back.

> You also need to watch out for cache maintenance when you do DMA.
> Not sure how much ends up being empty stubs when you compile for PBL.
> The code was written with the assumption of MMC controller being
> cache-coherent, which is only the case when caches are disabled.
>
> This means:
>
> - Explicit cache handling for streaming DMA
> - Coherent memory for consistent DMA

Right, and the generic helper would need coherent descriptors + streaming
sync to be correct on any MMU-on PBL.
For the record it is not what stalls us here: on the i.MX8M PBL path
the MMU is still off during load_bl33 (we enable it afterwards), so
the descriptor table should already be coherent.



Gruß,
Johannes